From 67dc02acc247396d988b36fba8344ed62ad4a4a8 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Mon, 30 Jun 2025 11:12:32 -0700 Subject: [PATCH] brw/reg_allocate: Only add interference for the source with the hazard shader-db: Lunar Lake total instructions in shared programs: 17105892 -> 17105732 (<.01%) instructions in affected programs: 55720 -> 55560 (-0.29%) helped: 29 / HURT: 24 total cycles in shared programs: 884342344 -> 884663448 (0.04%) cycles in affected programs: 154776382 -> 155097486 (0.21%) helped: 719 / HURT: 761 total spills in shared programs: 3278 -> 3262 (-0.49%) spills in affected programs: 320 -> 304 (-5.00%) helped: 4 /HURT: 0 total fills in shared programs: 1632 -> 1616 (-0.98%) fills in affected programs: 368 -> 352 (-4.35%) helped: 4 / HURT: 0 LOST: 3 GAINED: 4 No shader-db changes on any other Intel platforms. fossil-db: Lunar Lake Totals: Instrs: 208696275 -> 208692511 (-0.00%); split: -0.00%, +0.00% Cycle count: 31325252074 -> 31274118190 (-0.16%); split: -0.27%, +0.11% Spill count: 504809 -> 504472 (-0.07%); split: -0.07%, +0.01% Fill count: 607047 -> 606581 (-0.08%); split: -0.08%, +0.01% Scratch Memory Size: 35037184 -> 35001344 (-0.10%); split: -0.11%, +0.01% Totals from 44135 (6.24% of 707112) affected shaders: Instrs: 39570465 -> 39566701 (-0.01%); split: -0.01%, +0.00% Cycle count: 11140437886 -> 11089304002 (-0.46%); split: -0.76%, +0.30% Spill count: 279756 -> 279419 (-0.12%); split: -0.13%, +0.01% Fill count: 354706 -> 354240 (-0.13%); split: -0.14%, +0.01% Scratch Memory Size: 18758656 -> 18722816 (-0.19%); split: -0.20%, +0.01% Meteor Lake, DG2, Tiger Lake, Ice Lake, and Skylake had similar results. (Meteor Lake shown) Totals: Cycle count: 25377247343 -> 25377246251 (-0.00%); split: -0.00%, +0.00% Totals from 11 (0.00% of 806166) affected shaders: Cycle count: 899080 -> 897988 (-0.12%); split: -0.48%, +0.36% Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw_reg_allocate.cpp | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/src/intel/compiler/brw_reg_allocate.cpp b/src/intel/compiler/brw_reg_allocate.cpp index 48cfd8b36b5..d6d67974e5a 100644 --- a/src/intel/compiler/brw_reg_allocate.cpp +++ b/src/intel/compiler/brw_reg_allocate.cpp @@ -428,7 +428,7 @@ brw_reg_alloc::setup_live_interference(unsigned node, brw_range ip_range) * GRF sources and the destination. */ static bool -brw_inst_has_source_and_destination_hazard(const brw_inst *inst) +brw_inst_has_source_and_destination_hazard(const brw_inst *inst, unsigned src) { switch (inst->opcode) { case FS_OPCODE_PACK_HALF_2x16_SPLIT: @@ -506,14 +506,12 @@ brw_inst_has_source_and_destination_hazard(const brw_inst *inst) * would get stomped by the first decode as well. */ if (inst->exec_size == 16) { - for (int i = 0; i < inst->sources; i++) { - if (inst->src[i].file == VGRF && (inst->src[i].stride == 0 || - inst->src[i].type == BRW_TYPE_UW || - inst->src[i].type == BRW_TYPE_W || - inst->src[i].type == BRW_TYPE_UB || - inst->src[i].type == BRW_TYPE_B)) { - return true; - } + if (inst->src[src].file == VGRF && (inst->src[src].stride == 0 || + inst->src[src].type == BRW_TYPE_UW || + inst->src[src].type == BRW_TYPE_W || + inst->src[src].type == BRW_TYPE_UB || + inst->src[src].type == BRW_TYPE_B)) { + return true; } } return false; @@ -526,9 +524,10 @@ brw_reg_alloc::setup_inst_interference(const brw_inst *inst) /* Certain instructions can't safely use the same register for their * sources and destination. Add interference. */ - if (inst->dst.file == VGRF && brw_inst_has_source_and_destination_hazard(inst)) { + if (inst->dst.file == VGRF) { for (unsigned i = 0; i < inst->sources; i++) { - if (inst->src[i].file == VGRF) { + if (inst->src[i].file == VGRF && + brw_inst_has_source_and_destination_hazard(inst, i)) { ra_add_node_interference(g, first_vgrf_node + inst->dst.nr, first_vgrf_node + inst->src[i].nr); }