From 6785e42511d27b6832a49f99665483778a82ba36 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Tue, 13 May 2025 16:15:16 -0400 Subject: [PATCH] winsys/amdgpu: add a high priority gfx queue Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.cpp | 6 +++++- src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 1 + src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h | 1 + 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.cpp b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.cpp index c65a6d808a5..a6b89f00e38 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.cpp +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.cpp @@ -281,6 +281,7 @@ static struct radeon_winsys_ctx *amdgpu_ctx_create(struct radeon_winsys *rws, ctx->aws = amdgpu_winsys(rws); ctx->reference.count = 1; ctx->allow_context_lost = allow_context_lost; + ctx->priority = priority; dev = ctx->aws->dev; @@ -938,7 +939,10 @@ amdgpu_cs_create(struct radeon_cmdbuf *rcs, } else { switch (ip_type) { case AMD_IP_GFX: - acs->queue_index = AMDGPU_QUEUE_GFX; + if (ctx->priority >= RADEON_CTX_PRIORITY_HIGH) + acs->queue_index = AMDGPU_QUEUE_GFX_HIGH_PRIO; + else + acs->queue_index = AMDGPU_QUEUE_GFX; break; case AMD_IP_COMPUTE: acs->queue_index = AMDGPU_QUEUE_COMPUTE; diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h index bcbae0712eb..c655f8a33b9 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h @@ -38,6 +38,7 @@ struct amdgpu_ctx { /* Lost context status due to ioctl and allocation failures. */ enum pipe_reset_status sw_status; + enum radeon_ctx_priority priority; }; struct amdgpu_cs_buffer { diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h index ca391afb5d6..909c7fb8c85 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h @@ -119,6 +119,7 @@ struct amdgpu_screen_winsys { /* Queues using the fence ring. */ enum amdgpu_queue_index { AMDGPU_QUEUE_GFX, + AMDGPU_QUEUE_GFX_HIGH_PRIO, AMDGPU_QUEUE_COMPUTE, AMDGPU_QUEUE_SDMA, AMDGPU_MAX_QUEUES,