From 6773595ed0485afb49834d252e7b7e9849c8ad3f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 10 Nov 2023 19:02:49 -0500 Subject: [PATCH] nir: rename AMD XFB intrinsics to *_gfx11_amd to indicate it's only for gfx11. Acked-by: Alyssa Rosenzweig Part-of: --- src/amd/common/ac_nir_lower_ngg.c | 13 +++++++------ src/amd/compiler/aco_instruction_selection.cpp | 4 ++-- .../compiler/aco_instruction_selection_setup.cpp | 2 +- src/amd/llvm/ac_nir_to_llvm.c | 4 ++-- src/compiler/nir/nir_divergence_analysis.c | 4 ++-- src/compiler/nir/nir_intrinsics.py | 8 +++++--- 6 files changed, 19 insertions(+), 16 deletions(-) diff --git a/src/amd/common/ac_nir_lower_ngg.c b/src/amd/common/ac_nir_lower_ngg.c index b71cfcb5080..8045dd668c8 100644 --- a/src/amd/common/ac_nir_lower_ngg.c +++ b/src/amd/common/ac_nir_lower_ngg.c @@ -1885,9 +1885,10 @@ ngg_build_streamout_buffer_info(nir_builder *b, * ordered_id; Each buffer info is in a channel of a vec4. */ nir_def *buffer_offsets = - nir_ordered_xfb_counter_add_amd(b, ordered_id, nir_vec(b, workgroup_buffer_sizes, 4), - /* mask of buffers to update */ - .write_mask = info->buffers_written); + nir_ordered_xfb_counter_add_gfx11_amd(b, ordered_id, + nir_vec(b, workgroup_buffer_sizes, 4), + /* mask of buffers to update */ + .write_mask = info->buffers_written); nir_def *emit_prim[4]; memcpy(emit_prim, gen_prim, 4 * sizeof(nir_def *)); @@ -1933,9 +1934,9 @@ ngg_build_streamout_buffer_info(nir_builder *b, */ nir_if *if_any_overflow = nir_push_if(b, any_overflow); { - nir_xfb_counter_sub_amd(b, nir_vec(b, overflow_amount, 4), - /* mask of buffers to update */ - .write_mask = info->buffers_written); + nir_xfb_counter_sub_gfx11_amd(b, nir_vec(b, overflow_amount, 4), + /* mask of buffers to update */ + .write_mask = info->buffers_written); } nir_pop_if(b, if_any_overflow); diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 9c52e67d41f..ccb3515c394 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -9132,7 +9132,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) emit_split_vector(ctx, dst, dst.size()); break; } - case nir_intrinsic_ordered_xfb_counter_add_amd: { + case nir_intrinsic_ordered_xfb_counter_add_gfx11_amd: { Temp dst = get_ssa_temp(ctx, &instr->def); Temp ordered_id = get_ssa_temp(ctx, instr->src[0].ssa); Temp counter = get_ssa_temp(ctx, instr->src[1].ssa); @@ -9180,7 +9180,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) emit_split_vector(ctx, dst, instr->num_components); break; } - case nir_intrinsic_xfb_counter_sub_amd: { + case nir_intrinsic_xfb_counter_sub_gfx11_amd: { unsigned write_mask = nir_intrinsic_write_mask(instr); Temp counter = get_ssa_temp(ctx, instr->src[0].ssa); diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp index ec7a29e8d55..2c248ccc293 100644 --- a/src/amd/compiler/aco_instruction_selection_setup.cpp +++ b/src/amd/compiler/aco_instruction_selection_setup.cpp @@ -531,7 +531,7 @@ init_context(isel_context* ctx, nir_shader* shader) case nir_intrinsic_bvh64_intersect_ray_amd: case nir_intrinsic_load_vector_arg_amd: case nir_intrinsic_load_rt_dynamic_callable_stack_base_amd: - case nir_intrinsic_ordered_xfb_counter_add_amd: + case nir_intrinsic_ordered_xfb_counter_add_gfx11_amd: case nir_intrinsic_cmat_muladd_amd: type = RegType::vgpr; break; case nir_intrinsic_load_shared: case nir_intrinsic_load_shared2_amd: diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index ea2683b11c2..d96af75c1b5 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -3645,7 +3645,7 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md); break; } - case nir_intrinsic_ordered_xfb_counter_add_amd: { + case nir_intrinsic_ordered_xfb_counter_add_gfx11_amd: { /* must be called in a single lane of a workgroup. */ LLVMTypeRef gdsptr = LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS); @@ -3715,7 +3715,7 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins result = ac_build_gather_values(&ctx->ac, global_count, instr->num_components); break; } - case nir_intrinsic_xfb_counter_sub_amd: { + case nir_intrinsic_xfb_counter_sub_gfx11_amd: { /* must be called in a single lane of a workgroup. */ LLVMValueRef sub_vec = get_src(ctx, instr->src[0]); unsigned write_mask = nir_intrinsic_write_mask(instr); diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index b5f96e0b1c1..db7e90a27ea 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -630,8 +630,8 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state) case nir_intrinsic_load_btd_stack_id_intel: case nir_intrinsic_load_topology_id_intel: case nir_intrinsic_load_scratch_base_ptr: - case nir_intrinsic_ordered_xfb_counter_add_amd: - case nir_intrinsic_xfb_counter_sub_amd: + case nir_intrinsic_ordered_xfb_counter_add_gfx11_amd: + case nir_intrinsic_xfb_counter_sub_gfx11_amd: case nir_intrinsic_load_stack: case nir_intrinsic_load_ray_launch_id: case nir_intrinsic_load_ray_instance_custom_index: diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index e976ca5b01d..5bfbcd441c1 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -1678,15 +1678,17 @@ intrinsic("load_streamout_buffer_amd", dest_comp=4, indices=[BASE], bit_sizes=[3 # An ID for each workgroup ordered by primitve sequence system_value("ordered_id_amd", 1) -# Add src1 to global streamout buffer offsets in the specified order +# Add src1 to global streamout buffer offsets in the specified order. +# Only 1 lane must be active. # src[] = { ordered_id, counter } # WRITE_MASK = mask for counter channel to update -intrinsic("ordered_xfb_counter_add_amd", dest_comp=0, src_comp=[1, 0], indices=[WRITE_MASK], bit_sizes=[32]) +intrinsic("ordered_xfb_counter_add_gfx11_amd", dest_comp=0, src_comp=[1, 0], indices=[WRITE_MASK], bit_sizes=[32]) + # Subtract from global streamout buffer offsets. Used to fix up the offsets # when we overflow streamout buffers. # src[] = { offsets } # WRITE_MASK = mask of offsets to subtract -intrinsic("xfb_counter_sub_amd", src_comp=[0], indices=[WRITE_MASK], bit_sizes=[32]) +intrinsic("xfb_counter_sub_gfx11_amd", src_comp=[0], indices=[WRITE_MASK], bit_sizes=[32]) # Provoking vertex index in a primitive system_value("provoking_vtx_in_prim_amd", 1)