From 66bc9aec657d0838e5c71172c87131a3f24597e7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20=C5=9Alusarz?= <marcin.slusarz@intel.com>
Date: Fri, 15 Jul 2022 14:05:34 +0200
Subject: [PATCH] intel/compiler: add support for non-zero base in
 [load|store]_shared intrins
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Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17618>
---
 src/intel/compiler/brw_fs_nir.cpp | 26 ++++++++++++++++++++++----
 1 file changed, 22 insertions(+), 4 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index fa7eafda0a9..412184a4c9e 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -3884,12 +3884,21 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
 
    case nir_intrinsic_load_shared: {
       assert(devinfo->ver >= 7);
-      assert(nir_intrinsic_base(instr) == 0);
 
       const unsigned bit_size = nir_dest_bit_size(instr->dest);
       fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
       srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX7_BTI_SLM);
-      srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[0]);
+
+      fs_reg addr = get_nir_src(instr->src[0]);
+      int base = nir_intrinsic_base(instr);
+      if (base) {
+         fs_reg addr_off = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
+         bld.ADD(addr_off, addr, brw_imm_d(base));
+         srcs[SURFACE_LOGICAL_SRC_ADDRESS] = addr_off;
+      } else {
+         srcs[SURFACE_LOGICAL_SRC_ADDRESS] = addr;
+      }
+
       srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
       srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(0);
 
@@ -3921,12 +3930,21 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
 
    case nir_intrinsic_store_shared: {
       assert(devinfo->ver >= 7);
-      assert(nir_intrinsic_base(instr) == 0);
 
       const unsigned bit_size = nir_src_bit_size(instr->src[0]);
       fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
       srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX7_BTI_SLM);
-      srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[1]);
+
+      fs_reg addr = get_nir_src(instr->src[1]);
+      int base = nir_intrinsic_base(instr);
+      if (base) {
+         fs_reg addr_off = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
+         bld.ADD(addr_off, addr, brw_imm_d(base));
+         srcs[SURFACE_LOGICAL_SRC_ADDRESS] = addr_off;
+      } else {
+         srcs[SURFACE_LOGICAL_SRC_ADDRESS] = addr;
+      }
+
       srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
       /* No point in masking with sample mask, here we're handling compute
        * intrinsics.