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i965: clear global offset to zero in m0.2 for VS DP read.

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Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
This commit is contained in:
Zou Nan hai
2011-04-07 21:07:57 +08:00
parent 8800a798d1
commit 66b66295d0
1 changed files with 9 additions and 0 deletions
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src/mesa/drivers/dri/i965/brw_eu_emit.c
+9
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@@ -1759,6 +1759,11 @@ void brw_dp_READ_4_vs(struct brw_compile *p,
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_mask_control(p, BRW_MASK_DISABLE);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
/* M0.2 is global offset */
brw_MOV(p, retype(get_element(brw_message_reg(0), 2), BRW_REGISTER_TYPE_D),
brw_imm_d(0));
brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, msg_reg_nr, 2),
BRW_REGISTER_TYPE_UD),
brw_imm_ud(location));
@@ -1809,6 +1814,10 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p,
brw_set_mask_control(p, BRW_MASK_DISABLE);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
/* M0.2 is global offset */
brw_MOV(p, retype(get_element(brw_message_reg(0), 2), BRW_REGISTER_TYPE_D),
brw_imm_d(0));
/* M1.0 is block offset 0, M1.4 is block offset 1, all other
* fields ignored.
*/