From 656d7a0f881486634f83cdb7e03af94706f13119 Mon Sep 17 00:00:00 2001 From: Job Noorman Date: Tue, 22 Apr 2025 13:56:33 +0200 Subject: [PATCH] ir3: don't use VS input regs for binning variant This isn't necessary anymore since f6f7bc29 ("freedreno/a6xx: Program VFD_DEST_CNTL from program stateobj"). Allowing the binning variant to allocate its own inputs ensures we don't needlessly use high register numbers (and thus potentially have a larger register footprint). Unfortunately, this doesn't have an impact on waves on shaderdb/fossildb. Totals from 14669 (8.91% of 164575) affected shaders: Instrs: 3026564 -> 3024820 (-0.06%); split: -0.33%, +0.28% CodeSize: 6499538 -> 6496888 (-0.04%); split: -0.19%, +0.15% NOPs: 452142 -> 451590 (-0.12%); split: -1.76%, +1.64% MOVs: 67614 -> 66477 (-1.68%); split: -4.92%, +3.24% Full: 149240 -> 155922 (+4.48%); split: -0.76%, +5.24% (ss): 56452 -> 56247 (-0.36%); split: -4.58%, +4.22% (sy): 33366 -> 33535 (+0.51%); split: -2.82%, +3.33% (ss)-stall: 213221 -> 213992 (+0.36%); split: -0.87%, +1.23% (sy)-stall: 1391221 -> 1395187 (+0.29%); split: -4.05%, +4.34% Preamble Instrs: 695820 -> 695661 (-0.02%); split: -0.04%, +0.02% Cat0: 495109 -> 494450 (-0.13%); split: -1.65%, +1.52% Cat1: 127072 -> 125925 (-0.90%); split: -2.61%, +1.71% Cat7: 94725 -> 94787 (+0.07%); split: -0.08%, +0.15% Signed-off-by: Job Noorman Part-of: --- src/freedreno/ir3/ir3_compiler_nir.c | 35 +++------------------------- 1 file changed, 3 insertions(+), 32 deletions(-) diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index 44d3effa7ca..f5b38eb91be 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -5770,24 +5770,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler, ir3_debug_print(ir, "AFTER: ir3_sched"); - /* Pre-assign VS inputs on a6xx+ binning pass shader, to align - * with draw pass VS, so binning and draw pass can both use the - * same VBO state. - * - * Note that VS inputs are expected to be full precision. - */ - bool pre_assign_inputs = (ir->compiler->gen >= 6) && - (ir->type == MESA_SHADER_VERTEX) && - so->binning_pass; - - if (pre_assign_inputs) { - foreach_input (in, ir) { - assert(in->opc == OPC_META_INPUT); - unsigned inidx = in->input.inidx; - - in->dsts[0]->num = so->nonbinning->inputs[inidx].regid; - } - } else if (ctx->tcs_header) { + if (ctx->tcs_header) { /* We need to have these values in the same registers between VS and TCS * since the VS chains to TCS and doesn't get the sysvals redelivered. */ @@ -5869,20 +5852,8 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler, foreach_input (in, ir) { assert(in->opc == OPC_META_INPUT); unsigned inidx = in->input.inidx; - - if (pre_assign_inputs && !so->inputs[inidx].sysval) { - if (VALIDREG(so->nonbinning->inputs[inidx].regid)) { - compile_assert( - ctx, in->dsts[0]->num == so->nonbinning->inputs[inidx].regid); - compile_assert(ctx, !!(in->dsts[0]->flags & IR3_REG_HALF) == - so->nonbinning->inputs[inidx].half); - } - so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid; - so->inputs[inidx].half = so->nonbinning->inputs[inidx].half; - } else { - so->inputs[inidx].regid = in->dsts[0]->num; - so->inputs[inidx].half = !!(in->dsts[0]->flags & IR3_REG_HALF); - } + so->inputs[inidx].regid = in->dsts[0]->num; + so->inputs[inidx].half = !!(in->dsts[0]->flags & IR3_REG_HALF); } uint8_t clip_cull_mask = ctx->so->clip_mask | ctx->so->cull_mask;