diff --git a/src/asahi/lib/cmdbuf.xml b/src/asahi/lib/cmdbuf.xml index 257b3fa755b..3aeaea973a9 100644 --- a/src/asahi/lib/cmdbuf.xml +++ b/src/asahi/lib/cmdbuf.xml @@ -461,11 +461,8 @@ - - - - - + + @@ -476,15 +473,28 @@ - - - - - + + - + + + + + + + + + + + + + + + + diff --git a/src/asahi/lib/decode.c b/src/asahi/lib/decode.c index d84029d41aa..de67f83e493 100644 --- a/src/asahi/lib/decode.c +++ b/src/asahi/lib/decode.c @@ -422,14 +422,14 @@ agxdecode_record(uint64_t va, size_t size, bool verbose) assert(size == AGX_SET_INDEX_LENGTH); DUMP_CL(SET_INDEX, map, "Set index"); } else if (tag == 0x800000) { - assert(size == (AGX_BIND_PIPELINE_LENGTH - 4)); + assert(size == (AGX_BIND_FRAGMENT_PIPELINE_LENGTH - 4)); - agx_unpack(agxdecode_dump_stream, map, BIND_PIPELINE, cmd); + agx_unpack(agxdecode_dump_stream, map, BIND_FRAGMENT_PIPELINE, cmd); agxdecode_stateful(cmd.pipeline, "Pipeline", agxdecode_pipeline, verbose); /* TODO: parse */ - if (cmd.fs_varyings) { - uint8_t *map = agxdecode_fetch_gpu_mem(cmd.fs_varyings, 128); + if (cmd.varyings) { + uint8_t *map = agxdecode_fetch_gpu_mem(cmd.varyings, 128); hexdump(agxdecode_dump_stream, map, 128, false); DUMP_CL(VARYING_HEADER, map, "Varying header:"); @@ -441,7 +441,7 @@ agxdecode_record(uint64_t va, size_t size, bool verbose) } } - DUMP_UNPACKED(BIND_PIPELINE, cmd, "Bind fragment pipeline\n"); + DUMP_UNPACKED(BIND_FRAGMENT_PIPELINE, cmd, "Bind fragment pipeline\n"); } else if (size == 0) { pipeline_base = va; } else { @@ -459,10 +459,10 @@ agxdecode_cmd(const uint8_t *map, bool verbose) DUMP_UNPACKED(LAUNCH, cmd, "Launch\n"); return AGX_LAUNCH_LENGTH; } else if (map[0] == 0x2E && map[1] == 0x00 && map[2] == 0x00 && map[3] == 0x40) { - agx_unpack(agxdecode_dump_stream, map, BIND_PIPELINE, cmd); + agx_unpack(agxdecode_dump_stream, map, BIND_VERTEX_PIPELINE, cmd); agxdecode_stateful(cmd.pipeline, "Pipeline", agxdecode_pipeline, verbose); - DUMP_UNPACKED(BIND_PIPELINE, cmd, "Bind vertex pipeline\n"); - return AGX_BIND_PIPELINE_LENGTH; + DUMP_UNPACKED(BIND_VERTEX_PIPELINE, cmd, "Bind vertex pipeline\n"); + return AGX_BIND_VERTEX_PIPELINE_LENGTH; } else if (map[3] == 0x61) { DUMP_CL(DRAW, map, "Draw"); return AGX_DRAW_LENGTH; diff --git a/src/gallium/drivers/asahi/agx_state.c b/src/gallium/drivers/asahi/agx_state.c index edab8124c80..f156e087543 100644 --- a/src/gallium/drivers/asahi/agx_state.c +++ b/src/gallium/drivers/asahi/agx_state.c @@ -1359,17 +1359,16 @@ agx_build_store_pipeline(struct agx_context *ctx, uint32_t code, static uint64_t demo_launch_fragment(struct agx_context *ctx, struct agx_pool *pool, uint32_t pipeline, uint32_t varyings, unsigned input_count) { - struct agx_ptr t = agx_pool_alloc_aligned(pool, AGX_BIND_PIPELINE_LENGTH, 64); + struct agx_ptr t = agx_pool_alloc_aligned(pool, AGX_BIND_FRAGMENT_PIPELINE_LENGTH, 64); unsigned tex_count = ctx->stage[PIPE_SHADER_FRAGMENT].texture_count; - agx_pack(t.cpu, BIND_PIPELINE, cfg) { - cfg.tag = AGX_BIND_PIPELINE_FRAGMENT; + agx_pack(t.cpu, BIND_FRAGMENT_PIPELINE, cfg) { cfg.groups_of_8_immediate_textures = DIV_ROUND_UP(tex_count, 8); cfg.groups_of_4_samplers = DIV_ROUND_UP(tex_count, 4); cfg.more_than_4_textures = tex_count >= 4; cfg.input_count = input_count; cfg.pipeline = pipeline; - cfg.fs_varyings = varyings; + cfg.varyings = varyings; }; return t.gpu; @@ -1502,18 +1501,17 @@ agx_encode_state(struct agx_context *ctx, uint8_t *out, bool is_lines, bool is_points) { unsigned tex_count = ctx->stage[PIPE_SHADER_VERTEX].texture_count; - agx_pack(out, BIND_PIPELINE, cfg) { - cfg.tag = AGX_BIND_PIPELINE_VERTEX; + agx_pack(out, BIND_VERTEX_PIPELINE, cfg) { cfg.pipeline = pipeline_vertex; - cfg.vs_output_count_1 = ctx->vs->info.varyings.nr_slots; - cfg.vs_output_count_2 = ctx->vs->info.varyings.nr_slots; + cfg.output_count_1 = ctx->vs->info.varyings.nr_slots; + cfg.output_count_2 = ctx->vs->info.varyings.nr_slots; cfg.groups_of_8_immediate_textures = DIV_ROUND_UP(tex_count, 8); cfg.groups_of_4_samplers = DIV_ROUND_UP(tex_count, 4); cfg.more_than_4_textures = tex_count >= 4; } - out += AGX_BIND_PIPELINE_LENGTH; + out += AGX_BIND_VERTEX_PIPELINE_LENGTH; struct agx_pool *pool = &ctx->batch->pool; bool reads_tib = ctx->fs->info.reads_tib;