From 64fefc11793a60ad9800eb2943d9334e223288ba Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 16 May 2024 16:34:30 +0200 Subject: [PATCH] ac,radv,radeonsi: add a common helper for translating swizzle Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/common/ac_descriptors.c | 20 ++++++++ src/amd/common/ac_descriptors.h | 3 ++ src/amd/vulkan/radv_buffer_view.c | 5 +- src/amd/vulkan/radv_image.c | 19 ------- src/amd/vulkan/radv_image.h | 2 - src/amd/vulkan/radv_image_view.c | 8 +-- src/gallium/drivers/radeonsi/si_state.c | 66 +++++++++---------------- 7 files changed, 54 insertions(+), 69 deletions(-) diff --git a/src/amd/common/ac_descriptors.c b/src/amd/common/ac_descriptors.c index a6e72026c2e..b951e490d03 100644 --- a/src/amd/common/ac_descriptors.c +++ b/src/amd/common/ac_descriptors.c @@ -11,6 +11,26 @@ #include "sid.h" #include "util/u_math.h" +#include "util/format/u_format.h" + +unsigned +ac_map_swizzle(unsigned swizzle) +{ + switch (swizzle) { + case PIPE_SWIZZLE_Y: + return V_008F0C_SQ_SEL_Y; + case PIPE_SWIZZLE_Z: + return V_008F0C_SQ_SEL_Z; + case PIPE_SWIZZLE_W: + return V_008F0C_SQ_SEL_W; + case PIPE_SWIZZLE_0: + return V_008F0C_SQ_SEL_0; + case PIPE_SWIZZLE_1: + return V_008F0C_SQ_SEL_1; + default: /* PIPE_SWIZZLE_X */ + return V_008F0C_SQ_SEL_X; + } +} void ac_build_sampler_descriptor(const enum amd_gfx_level gfx_level, const struct ac_sampler_state *state, uint32_t desc[4]) diff --git a/src/amd/common/ac_descriptors.h b/src/amd/common/ac_descriptors.h index f2c4320dbe1..ebdd39189f9 100644 --- a/src/amd/common/ac_descriptors.h +++ b/src/amd/common/ac_descriptors.h @@ -15,6 +15,9 @@ extern "C" { #endif +unsigned +ac_map_swizzle(unsigned swizzle); + struct ac_sampler_state { unsigned address_mode_u : 3; unsigned address_mode_v : 3; diff --git a/src/amd/vulkan/radv_buffer_view.c b/src/amd/vulkan/radv_buffer_view.c index 34627b94443..296c4d75e02 100644 --- a/src/amd/vulkan/radv_buffer_view.c +++ b/src/amd/vulkan/radv_buffer_view.c @@ -8,6 +8,7 @@ * SPDX-License-Identifier: MIT */ +#include "ac_descriptors.h" #include "gfx10_format_table.h" #include "radv_buffer.h" @@ -42,8 +43,8 @@ radv_make_texel_buffer_descriptor(struct radv_device *device, uint64_t va, VkFor range /= stride; } - rsrc_word3 = S_008F0C_DST_SEL_X(radv_map_swizzle(swizzle[0])) | S_008F0C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) | - S_008F0C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) | S_008F0C_DST_SEL_W(radv_map_swizzle(swizzle[3])); + rsrc_word3 = S_008F0C_DST_SEL_X(ac_map_swizzle(swizzle[0])) | S_008F0C_DST_SEL_Y(ac_map_swizzle(swizzle[1])) | + S_008F0C_DST_SEL_Z(ac_map_swizzle(swizzle[2])) | S_008F0C_DST_SEL_W(ac_map_swizzle(swizzle[3])); if (pdev->info.gfx_level >= GFX10) { const struct gfx10_format *fmt = &ac_get_gfx10_format_table(&pdev->info)[vk_format_to_pipe_format(vk_format)]; diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 457a00605b4..274026c05fa 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -715,25 +715,6 @@ radv_get_surface_flags(struct radv_device *device, struct radv_image *image, uns return flags; } -unsigned -radv_map_swizzle(unsigned swizzle) -{ - switch (swizzle) { - case PIPE_SWIZZLE_Y: - return V_008F0C_SQ_SEL_Y; - case PIPE_SWIZZLE_Z: - return V_008F0C_SQ_SEL_Z; - case PIPE_SWIZZLE_W: - return V_008F0C_SQ_SEL_W; - case PIPE_SWIZZLE_0: - return V_008F0C_SQ_SEL_0; - case PIPE_SWIZZLE_1: - return V_008F0C_SQ_SEL_1; - default: /* PIPE_SWIZZLE_X */ - return V_008F0C_SQ_SEL_X; - } -} - void radv_compose_swizzle(const struct util_format_description *desc, const VkComponentMapping *mapping, enum pipe_swizzle swizzle[4]) diff --git a/src/amd/vulkan/radv_image.h b/src/amd/vulkan/radv_image.h index 92cd3bb8de7..46e8f58f357 100644 --- a/src/amd/vulkan/radv_image.h +++ b/src/amd/vulkan/radv_image.h @@ -311,8 +311,6 @@ bool radv_image_use_dcc_image_stores(const struct radv_device *device, const str bool radv_image_use_dcc_predication(const struct radv_device *device, const struct radv_image *image); -unsigned radv_map_swizzle(unsigned swizzle); - void radv_compose_swizzle(const struct util_format_description *desc, const VkComponentMapping *mapping, enum pipe_swizzle swizzle[4]); diff --git a/src/amd/vulkan/radv_image_view.c b/src/amd/vulkan/radv_image_view.c index 0b06af8ad63..f06e0275893 100644 --- a/src/amd/vulkan/radv_image_view.c +++ b/src/amd/vulkan/radv_image_view.c @@ -161,8 +161,8 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima state[1] = S_00A004_FORMAT_GFX10(img_format) | S_00A004_WIDTH_LO(width - 1); state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) | S_00A008_HEIGHT(height - 1) | S_00A008_RESOURCE_LEVEL(pdev->info.gfx_level < GFX11); - state[3] = S_00A00C_DST_SEL_X(radv_map_swizzle(swizzle[0])) | S_00A00C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) | - S_00A00C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) | S_00A00C_DST_SEL_W(radv_map_swizzle(swizzle[3])) | + state[3] = S_00A00C_DST_SEL_X(ac_map_swizzle(swizzle[0])) | S_00A00C_DST_SEL_Y(ac_map_swizzle(swizzle[1])) | + S_00A00C_DST_SEL_Z(ac_map_swizzle(swizzle[2])) | S_00A00C_DST_SEL_W(ac_map_swizzle(swizzle[3])) | S_00A00C_BASE_LEVEL(image->vk.samples > 1 ? 0 : first_level) | S_00A00C_LAST_LEVEL_GFX10(image->vk.samples > 1 ? util_logbase2(image->vk.samples) : last_level) | S_00A00C_BC_SWIZZLE(ac_border_color_swizzle(desc)) | S_00A00C_TYPE(type); @@ -297,8 +297,8 @@ gfx6_make_texture_descriptor(struct radv_device *device, struct radv_image *imag state[1] = (S_008F14_MIN_LOD(util_unsigned_fixed(CLAMP(min_lod, 0, 15), 8)) | S_008F14_DATA_FORMAT(data_format) | S_008F14_NUM_FORMAT(num_format)); state[2] = (S_008F18_WIDTH(width - 1) | S_008F18_HEIGHT(height - 1) | S_008F18_PERF_MOD(4)); - state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) | S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) | - S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) | S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) | + state[3] = (S_008F1C_DST_SEL_X(ac_map_swizzle(swizzle[0])) | S_008F1C_DST_SEL_Y(ac_map_swizzle(swizzle[1])) | + S_008F1C_DST_SEL_Z(ac_map_swizzle(swizzle[2])) | S_008F1C_DST_SEL_W(ac_map_swizzle(swizzle[3])) | S_008F1C_BASE_LEVEL(image->vk.samples > 1 ? 0 : first_level) | S_008F1C_LAST_LEVEL(image->vk.samples > 1 ? util_logbase2(image->vk.samples) : last_level) | S_008F1C_TYPE(type)); diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 578aec91e3d..fcb2d4f87fe 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -22,24 +22,6 @@ #include "ac_formats.h" #include "gfx10_format_table.h" -static unsigned si_map_swizzle(unsigned swizzle) -{ - switch (swizzle) { - case PIPE_SWIZZLE_Y: - return V_008F0C_SQ_SEL_Y; - case PIPE_SWIZZLE_Z: - return V_008F0C_SQ_SEL_Z; - case PIPE_SWIZZLE_W: - return V_008F0C_SQ_SEL_W; - case PIPE_SWIZZLE_0: - return V_008F0C_SQ_SEL_0; - case PIPE_SWIZZLE_1: - return V_008F0C_SQ_SEL_1; - default: /* PIPE_SWIZZLE_X */ - return V_008F0C_SQ_SEL_X; - } -} - /* 12.4 fixed-point */ static unsigned si_pack_float_12p4(float x) { @@ -4442,10 +4424,10 @@ void si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf state[4] = 0; state[5] = S_008F04_STRIDE(stride); state[6] = num_records; - state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) | - S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) | - S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) | - S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])); + state[7] = S_008F0C_DST_SEL_X(ac_map_swizzle(desc->swizzle[0])) | + S_008F0C_DST_SEL_Y(ac_map_swizzle(desc->swizzle[1])) | + S_008F0C_DST_SEL_Z(ac_map_swizzle(desc->swizzle[2])) | + S_008F0C_DST_SEL_W(ac_map_swizzle(desc->swizzle[3])); if (screen->info.gfx_level >= GFX10) { const struct gfx10_format *fmt = &ac_get_gfx10_format_table(&screen->info)[format]; @@ -4555,10 +4537,10 @@ static void cdna_emu_make_image_descriptor(struct si_screen *screen, struct si_t state[0] = 0; state[1] = S_008F04_STRIDE(stride); state[2] = num_records; - state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) | - S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) | - S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) | - S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])); + state[3] = S_008F0C_DST_SEL_X(ac_map_swizzle(swizzle[0])) | + S_008F0C_DST_SEL_Y(ac_map_swizzle(swizzle[1])) | + S_008F0C_DST_SEL_Z(ac_map_swizzle(swizzle[2])) | + S_008F0C_DST_SEL_W(ac_map_swizzle(swizzle[3])); if (screen->info.gfx_level >= GFX10) { const struct gfx10_format *fmt = &ac_get_gfx10_format_table(&screen->info)[pipe_format]; @@ -4679,10 +4661,10 @@ static void gfx10_make_texture_descriptor( S_00A004_WIDTH_LO(width - 1); state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) | S_00A008_HEIGHT(height - 1); - state[3] = S_00A00C_DST_SEL_X(si_map_swizzle(swizzle[0])) | - S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle[1])) | - S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle[2])) | - S_00A00C_DST_SEL_W(si_map_swizzle(swizzle[3])) | + state[3] = S_00A00C_DST_SEL_X(ac_map_swizzle(swizzle[0])) | + S_00A00C_DST_SEL_Y(ac_map_swizzle(swizzle[1])) | + S_00A00C_DST_SEL_Z(ac_map_swizzle(swizzle[2])) | + S_00A00C_DST_SEL_W(ac_map_swizzle(swizzle[3])) | S_00A00C_NO_EDGE_CLAMP(res->last_level > 0 && util_format_is_compressed(res->format) && !util_format_is_compressed(pipe_format)) | @@ -4706,10 +4688,10 @@ static void gfx10_make_texture_descriptor( S_00A008_RESOURCE_LEVEL(screen->info.gfx_level < GFX11); state[3] = - S_00A00C_DST_SEL_X(si_map_swizzle(swizzle[0])) | - S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle[1])) | - S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle[2])) | - S_00A00C_DST_SEL_W(si_map_swizzle(swizzle[3])) | + S_00A00C_DST_SEL_X(ac_map_swizzle(swizzle[0])) | + S_00A00C_DST_SEL_Y(ac_map_swizzle(swizzle[1])) | + S_00A00C_DST_SEL_Z(ac_map_swizzle(swizzle[2])) | + S_00A00C_DST_SEL_W(ac_map_swizzle(swizzle[3])) | S_00A00C_BASE_LEVEL(res->nr_samples > 1 ? 0 : first_level) | S_00A00C_LAST_LEVEL_GFX10(res->nr_samples > 1 ? util_logbase2(res->nr_samples) : last_level) | S_00A00C_BC_SWIZZLE(ac_border_color_swizzle(desc)) | S_00A00C_TYPE(type); @@ -4857,10 +4839,10 @@ static void si_make_texture_descriptor(struct si_screen *screen, struct si_textu state[0] = 0; state[1] = (S_008F14_DATA_FORMAT(data_format) | S_008F14_NUM_FORMAT(num_format)); state[2] = (S_008F18_WIDTH(width - 1) | S_008F18_HEIGHT(height - 1) | S_008F18_PERF_MOD(4)); - state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) | - S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) | - S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) | - S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) | + state[3] = (S_008F1C_DST_SEL_X(ac_map_swizzle(swizzle[0])) | + S_008F1C_DST_SEL_Y(ac_map_swizzle(swizzle[1])) | + S_008F1C_DST_SEL_Z(ac_map_swizzle(swizzle[2])) | + S_008F1C_DST_SEL_W(ac_map_swizzle(swizzle[3])) | S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) | S_008F1C_LAST_LEVEL(num_samples > 1 ? util_logbase2(num_samples) : last_level) | S_008F1C_TYPE(type)); @@ -5474,10 +5456,10 @@ static void *si_create_vertex_elements(struct pipe_context *ctx, unsigned count, v->vb_alignment_check_mask |= 1 << vbo_index; } - v->elem[i].rsrc_word3 = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) | - S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) | - S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) | - S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])); + v->elem[i].rsrc_word3 = S_008F0C_DST_SEL_X(ac_map_swizzle(desc->swizzle[0])) | + S_008F0C_DST_SEL_Y(ac_map_swizzle(desc->swizzle[1])) | + S_008F0C_DST_SEL_Z(ac_map_swizzle(desc->swizzle[2])) | + S_008F0C_DST_SEL_W(ac_map_swizzle(desc->swizzle[3])); if (sscreen->info.gfx_level >= GFX10) { const struct gfx10_format *fmt = &ac_get_gfx10_format_table(&sscreen->info)[elements[i].src_format];