From 63f7a03dd1bd954bd448f667c3bda3e8b4d2498c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20Sch=C3=BCrmann?= Date: Tue, 15 Jul 2025 10:50:04 +0200 Subject: [PATCH] ac/nir: use HW-requirements on alignment for vectorizing LDS Totals from 663 (0.83% of 79839) affected shaders: (Navi48) MaxWaves: 16758 -> 16752 (-0.04%) Instrs: 748063 -> 750213 (+0.29%); split: -0.08%, +0.37% CodeSize: 3864912 -> 3874984 (+0.26%); split: -0.11%, +0.37% VGPRs: 40640 -> 40604 (-0.09%); split: -0.30%, +0.21% Latency: 6977888 -> 6980523 (+0.04%); split: -0.05%, +0.09% InvThroughput: 1176313 -> 1174557 (-0.15%); split: -0.23%, +0.08% VClause: 13852 -> 13843 (-0.06%); split: -0.10%, +0.04% SClause: 13221 -> 13219 (-0.02%) Copies: 44814 -> 44760 (-0.12%); split: -0.41%, +0.29% PreSGPRs: 29276 -> 29285 (+0.03%) PreVGPRs: 30835 -> 30861 (+0.08%); split: -0.11%, +0.19% VALU: 423942 -> 423782 (-0.04%); split: -0.21%, +0.17% SALU: 81271 -> 81188 (-0.10%); split: -0.19%, +0.09% VOPD: 243 -> 238 (-2.06%) Part-of: --- src/amd/common/nir/ac_nir.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/src/amd/common/nir/ac_nir.c b/src/amd/common/nir/ac_nir.c index 65628dbfb8a..210555cc31e 100644 --- a/src/amd/common/nir/ac_nir.c +++ b/src/amd/common/nir/ac_nir.c @@ -594,11 +594,7 @@ ac_nir_mem_vectorize_callback(unsigned align_mul, unsigned align_offset, unsigne return false; } - uint32_t align; - if (align_offset) - align = 1 << (ffs(align_offset) - 1); - else - align = align_mul; + uint32_t align = nir_combined_align(align_mul, align_offset); /* Don't cross swizzle elements. stack/scratch intrinsics use scratch_* instructions, which * seem to work fine. @@ -620,10 +616,9 @@ ac_nir_mem_vectorize_callback(unsigned align_mul, unsigned align_offset, unsigne /* AMD hardware can't do 3-component loads except for 96-bit loads. */ return bit_size == 32 && align % 16 == 0; } - unsigned req = bit_size >= 32 ? bit_size * num_components : bit_size; - if (req == 64 || req == 128) /* 64-bit and 128-bit loads can use ds_read2_b{32,64} */ - req /= 2u; - return align % (req / 8u) == 0; + + /* DS loads and stores require the alignment of the size. */ + return align % (aligned_new_size / 8u) == 0; } return false; }