From 63b5b93dd315ed8794f0e15b5ce93acb9db66e06 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 2 May 2023 11:21:08 +0200 Subject: [PATCH] radv: replace radv_get_levelCount() by vk_image_subresource_level_count() Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/meta/radv_meta_clear.c | 12 ++++++------ src/amd/vulkan/meta/radv_meta_decompress.c | 4 ++-- src/amd/vulkan/meta/radv_meta_fast_clear.c | 4 ++-- src/amd/vulkan/radv_cmd_buffer.c | 10 +++++----- src/amd/vulkan/radv_private.h | 7 ------- 5 files changed, 15 insertions(+), 22 deletions(-) diff --git a/src/amd/vulkan/meta/radv_meta_clear.c b/src/amd/vulkan/meta/radv_meta_clear.c index 2d0ab579bba..25a5f643b9f 100644 --- a/src/amd/vulkan/meta/radv_meta_clear.c +++ b/src/amd/vulkan/meta/radv_meta_clear.c @@ -1250,7 +1250,7 @@ radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, uint64_t size; /* MSAA images do not support mipmap levels. */ - assert(range->baseMipLevel == 0 && radv_get_levelCount(image, range) == 1); + assert(range->baseMipLevel == 0 && vk_image_subresource_level_count(&image->vk, range) == 1); offset += slice_size * range->baseArrayLayer; size = slice_size * vk_image_subresource_layer_count(&image->vk, range); @@ -1263,7 +1263,7 @@ uint32_t radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, const VkImageSubresourceRange *range, uint32_t value) { - uint32_t level_count = radv_get_levelCount(image, range); + uint32_t level_count = vk_image_subresource_level_count(&image->vk, range); uint32_t layer_count = vk_image_subresource_layer_count(&image->vk, range); uint32_t flush_bits = 0; @@ -1354,7 +1354,7 @@ radv_clear_dcc_comp_to_single(struct radv_cmd_buffer *cmd_buffer, radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, pipeline); - for (uint32_t l = 0; l < radv_get_levelCount(image, range); l++) { + for (uint32_t l = 0; l < vk_image_subresource_level_count(&image->vk, range); l++) { uint32_t width, height; /* Do not write the clear color value for levels without DCC. */ @@ -1428,7 +1428,7 @@ uint32_t radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image, const VkImageSubresourceRange *range, uint32_t value) { - uint32_t level_count = radv_get_levelCount(image, range); + uint32_t level_count = vk_image_subresource_level_count(&image->vk, range); uint32_t flush_bits = 0; uint32_t htile_mask; @@ -2113,7 +2113,7 @@ radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer, struct radv_image *ima { .aspectMask = range->aspectMask, .baseMipLevel = range->baseMipLevel, - .levelCount = radv_get_levelCount(image, range), + .levelCount = vk_image_subresource_level_count(&image->vk, range), .baseArrayLayer = range->baseArrayLayer, .layerCount = vk_image_subresource_layer_count(&image->vk, range), }, @@ -2217,7 +2217,7 @@ radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *imag continue; } - for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) { + for (uint32_t l = 0; l < vk_image_subresource_level_count(&image->vk, range); ++l) { const uint32_t layer_count = image->vk.image_type == VK_IMAGE_TYPE_3D ? radv_minify(image->info.depth, range->baseMipLevel + l) : vk_image_subresource_layer_count(&image->vk, range); diff --git a/src/amd/vulkan/meta/radv_meta_decompress.c b/src/amd/vulkan/meta/radv_meta_decompress.c index 7812c8bdd49..33cd2a7ac31 100644 --- a/src/amd/vulkan/meta/radv_meta_decompress.c +++ b/src/amd/vulkan/meta/radv_meta_decompress.c @@ -492,7 +492,7 @@ radv_process_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image }); } - for (uint32_t l = 0; l < radv_get_levelCount(image, subresourceRange); ++l) { + for (uint32_t l = 0; l < vk_image_subresource_level_count(&image->vk, subresourceRange); ++l) { /* Do not decompress levels without HTILE. */ if (!radv_htile_enabled(image, subresourceRange->baseMipLevel + l)) @@ -543,7 +543,7 @@ radv_expand_depth_stencil_compute(struct radv_cmd_buffer *cmd_buffer, struct rad radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, device->meta_state.expand_depth_stencil_compute_pipeline); - for (uint32_t l = 0; l < radv_get_levelCount(image, subresourceRange); l++) { + for (uint32_t l = 0; l < vk_image_subresource_level_count(&image->vk, subresourceRange); l++) { uint32_t width, height; /* Do not decompress levels without HTILE. */ diff --git a/src/amd/vulkan/meta/radv_meta_fast_clear.c b/src/amd/vulkan/meta/radv_meta_fast_clear.c index c9b156505a3..abec0b4ae51 100644 --- a/src/amd/vulkan/meta/radv_meta_fast_clear.c +++ b/src/amd/vulkan/meta/radv_meta_fast_clear.c @@ -605,7 +605,7 @@ radv_process_color_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image * radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_GRAPHICS, *pipeline); - for (uint32_t l = 0; l < radv_get_levelCount(image, subresourceRange); ++l) { + for (uint32_t l = 0; l < vk_image_subresource_level_count(&image->vk, subresourceRange); ++l) { uint32_t width, height; /* Do not decompress levels without DCC. */ @@ -736,7 +736,7 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer, struct radv_imag radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, device->meta_state.fast_clear_flush.dcc_decompress_compute_pipeline); - for (uint32_t l = 0; l < radv_get_levelCount(image, subresourceRange); l++) { + for (uint32_t l = 0; l < vk_image_subresource_level_count(&image->vk, subresourceRange); l++) { uint32_t width, height; /* Do not decompress levels without DCC. */ diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 2ebc3c562e4..4900981d9ce 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2984,7 +2984,7 @@ radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image VkClearDepthStencilValue ds_clear_value, VkImageAspectFlags aspects) { struct radeon_cmdbuf *cs = cmd_buffer->cs; - uint32_t level_count = radv_get_levelCount(image, range); + uint32_t level_count = vk_image_subresource_level_count(&image->vk, range); if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) { uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel); @@ -3036,7 +3036,7 @@ radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer, struct ra return; uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel); - uint32_t level_count = radv_get_levelCount(image, range); + uint32_t level_count = vk_image_subresource_level_count(&image->vk, range); radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating)); radeon_emit(cs, S_370_DST_SEL(V_370_MEM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(V_370_PFP)); @@ -3156,7 +3156,7 @@ radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image * uint64_t pred_val = value; uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel); - uint32_t level_count = radv_get_levelCount(image, range); + uint32_t level_count = vk_image_subresource_level_count(&image->vk, range); uint32_t count = 2 * level_count; ASSERTED unsigned cdw_max = @@ -3188,7 +3188,7 @@ radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image * uint64_t pred_val = value; uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel); - uint32_t level_count = radv_get_levelCount(image, range); + uint32_t level_count = vk_image_subresource_level_count(&image->vk, range); uint32_t count = 2 * level_count; assert(radv_dcc_enabled(image, range->baseMipLevel)); @@ -3244,7 +3244,7 @@ radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_im const VkImageSubresourceRange *range, uint32_t color_values[2]) { struct radeon_cmdbuf *cs = cmd_buffer->cs; - uint32_t level_count = radv_get_levelCount(image, range); + uint32_t level_count = vk_image_subresource_level_count(&image->vk, range); uint32_t count = 2 * level_count; assert(radv_image_has_cmask(image) || radv_dcc_enabled(image, range->baseMipLevel)); diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 93c8954f998..4d36407e18a 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2798,13 +2798,6 @@ unsigned radv_image_queue_family_mask(const struct radv_image *image, enum radv_queue_family family, enum radv_queue_family queue_family); -static inline uint32_t -radv_get_levelCount(const struct radv_image *image, const VkImageSubresourceRange *range) -{ - return range->levelCount == VK_REMAINING_MIP_LEVELS ? image->info.levels - range->baseMipLevel - : range->levelCount; -} - bool radv_image_is_renderable(struct radv_device *device, struct radv_image *image); struct radeon_bo_metadata;