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freedreno: extract vsc pipe bo from GMEM state

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Prep work for reorganizing GMEM state and extracting out of fd_context.
The vsc pipe bo was the one thing that doesn't change with GMEM/tile
config.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
This commit is contained in:
Rob Clark
2020-01-21 10:34:29 -08:00
committed by Marge Bot
parent d5c32db076
commit 62c10b395e
7 changed files with 32 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
+8 -10
View File
@@ -583,16 +583,14 @@ fd2_emit_tile_init(struct fd_batch *batch)
OUT_RING(ring, 0x0000000C);
for (int i = 0; i < gmem->num_vsc_pipes; i++) {
struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
/* allocate in 64k increments to avoid reallocs */
uint32_t bo_size = align(batch->num_vertices, 0x10000);
if (!pipe->bo || fd_bo_size(pipe->bo) < bo_size) {
if (pipe->bo)
fd_bo_del(pipe->bo);
pipe->bo = fd_bo_new(ctx->dev, bo_size,
if (!ctx->vsc_pipe_bo[i] || fd_bo_size(ctx->vsc_pipe_bo[i]) < bo_size) {
if (ctx->vsc_pipe_bo[i])
fd_bo_del(ctx->vsc_pipe_bo[i]);
ctx->vsc_pipe_bo[i] = fd_bo_new(ctx->dev, bo_size,
DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_pipe[%u]", i);
assert(pipe->bo);
assert(ctx->vsc_pipe_bo[i]);
}
/* memory export address (export32):
@@ -601,7 +599,7 @@ fd2_emit_tile_init(struct fd_batch *batch)
* .z: 0x4B00D000 (?)
* .w: 0x4B000000 (?) | max_index (?)
*/
OUT_RELOCW(ring, pipe->bo, 0, 0x40000000, -2);
OUT_RELOCW(ring, ctx->vsc_pipe_bo[i], 0, 0x40000000, -2);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x4B00D000);
OUT_RING(ring, 0x4B000000 | bo_size);
@@ -723,7 +721,7 @@ fd2_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
}
if (use_hw_binning(batch)) {
struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];
struct fd_bo *pipe_bo = ctx->vsc_pipe_bo[tile->p];
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_VGT_CURRENT_BIN_ID_MIN));
@@ -735,7 +733,7 @@ fd2_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
/* TODO only emit this when tile->p changes */
OUT_PKT3(ring, CP_SET_DRAW_INIT_FLAGS, 1);
OUT_RELOC(ring, pipe->bo, 0, 0, 0);
OUT_RELOC(ring, pipe_bo, 0, 0, 0);
}
}
src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
+6 -5
View File
@@ -787,8 +787,8 @@ update_vsc_pipe(struct fd_batch *batch)
for (i = 0; i < 8; i++) {
struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
if (!pipe->bo) {
pipe->bo = fd_bo_new(ctx->dev, 0x40000,
if (!ctx->vsc_pipe_bo[i]) {
ctx->vsc_pipe_bo[i] = fd_bo_new(ctx->dev, 0x40000,
DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_pipe[%u]", i);
}
@@ -797,8 +797,8 @@ update_vsc_pipe(struct fd_batch *batch)
A3XX_VSC_PIPE_CONFIG_Y(pipe->y) |
A3XX_VSC_PIPE_CONFIG_W(pipe->w) |
A3XX_VSC_PIPE_CONFIG_H(pipe->h));
OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE[i].DATA_ADDRESS */
OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE[i].DATA_LENGTH */
OUT_RELOCW(ring, ctx->vsc_pipe_bo[i], 0, 0, 0); /* VSC_PIPE[i].DATA_ADDRESS */
OUT_RING(ring, fd_bo_size(ctx->vsc_pipe_bo[i]) - 32); /* VSC_PIPE[i].DATA_LENGTH */
}
}
@@ -1019,6 +1019,7 @@ fd3_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
if (use_hw_binning(batch)) {
struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];
struct fd_bo *pipe_bo = ctx->vsc_pipe_bo[tile->p];
assert(pipe->w && pipe->h);
@@ -1031,7 +1032,7 @@ fd3_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
OUT_RELOCW(ring, pipe_bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
(tile->p * 4), 0, 0);
} else {
src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
+6 -7
View File
@@ -579,18 +579,16 @@ update_vsc_pipe(struct fd_batch *batch)
OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(0), 8);
for (i = 0; i < 8; i++) {
struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
if (!pipe->bo) {
pipe->bo = fd_bo_new(ctx->dev, 0x40000,
if (!ctx->vsc_pipe_bo[i]) {
ctx->vsc_pipe_bo[i] = fd_bo_new(ctx->dev, 0x40000,
DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_pipe[%u]", i);
}
OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i] */
OUT_RELOCW(ring, ctx->vsc_pipe_bo[i], 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i] */
}
OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(0), 8);
for (i = 0; i < 8; i++) {
struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
OUT_RING(ring, fd_bo_size(ctx->vsc_pipe_bo[i]) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
}
}
@@ -769,6 +767,7 @@ fd4_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
if (use_hw_binning(batch)) {
struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];
struct fd_bo *pipe_bo = ctx->vsc_pipe_bo[tile->p];
assert(pipe->w && pipe->h);
@@ -780,7 +779,7 @@ fd4_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
A4XX_PC_VSTREAM_CONTROL_N(tile->n));
OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
OUT_RELOCW(ring, pipe_bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
OUT_RELOCW(ring, fd4_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
(tile->p * 4), 0, 0);
} else {
src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
+6 -7
View File
@@ -286,18 +286,16 @@ update_vsc_pipe(struct fd_batch *batch)
OUT_PKT4(ring, REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(0), 32);
for (i = 0; i < 16; i++) {
struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
if (!pipe->bo) {
pipe->bo = fd_bo_new(ctx->dev, 0x20000,
if (!ctx->vsc_pipe_bo[i]) {
ctx->vsc_pipe_bo[i] = fd_bo_new(ctx->dev, 0x20000,
DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_pipe[%u]", i);
}
OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i].LO/HI */
OUT_RELOCW(ring, ctx->vsc_pipe_bo[i], 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i].LO/HI */
}
OUT_PKT4(ring, REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(0), 16);
for (i = 0; i < 16; i++) {
struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
OUT_RING(ring, fd_bo_size(ctx->vsc_pipe_bo[i]) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
}
}
@@ -437,6 +435,7 @@ fd5_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
if (use_hw_binning(batch)) {
struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];
struct fd_bo *pipe_bo = ctx->vsc_pipe_bo[tile->p];
OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
@@ -446,7 +445,7 @@ fd5_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
OUT_PKT7(ring, CP_SET_BIN_DATA5, 5);
OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
CP_SET_BIN_DATA5_0_VSC_N(tile->n));
OUT_RELOC(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE[p].DATA_ADDRESS */
OUT_RELOC(ring, pipe_bo, 0, 0, 0); /* VSC_PIPE[p].DATA_ADDRESS */
OUT_RELOC(ring, fd5_ctx->vsc_size_mem, /* VSC_SIZE_ADDRESS + (p * 4) */
(tile->p * 4), 0, 0);
} else {
src/gallium/drivers/freedreno/freedreno_context.c
+3 -4
View File
@@ -193,11 +193,10 @@ fd_context_destroy(struct pipe_context *pctx)
slab_destroy_child(&ctx->transfer_pool);
for (i = 0; i < ARRAY_SIZE(ctx->vsc_pipe); i++) {
struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
if (!pipe->bo)
for (i = 0; i < ARRAY_SIZE(ctx->vsc_pipe_bo); i++) {
if (!ctx->vsc_pipe_bo[i])
break;
fd_bo_del(pipe->bo);
fd_bo_del(ctx->vsc_pipe_bo[i]);
}
fd_device_del(ctx->dev);
src/gallium/drivers/freedreno/freedreno_context.h
+3
View File
@@ -269,6 +269,9 @@ struct fd_context {
struct fd_vsc_pipe vsc_pipe[32];
struct fd_tile tile[512];
/* Per vsc pipe bo's (a2xx-a5xx): */
struct fd_bo *vsc_pipe_bo[32];
/* which state objects need to be re-emit'd: */
enum fd_dirty_3d_state dirty;
src/gallium/drivers/freedreno/freedreno_gmem.h
-2
View File
@@ -33,8 +33,6 @@
/* per-pipe configuration for hw binning: */
struct fd_vsc_pipe {
// TODO a3xx/a4xx/a5xx could probably move to single bo for vsc stream, like a6xx does
struct fd_bo *bo;
uint8_t x, y, w, h; /* VSC_PIPE[p].CONFIG */
};