radeonsi: set better tessellation tunables on gfx9 and gfx10
same as PAL Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143>
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@@ -5670,7 +5670,14 @@ static void si_init_config(struct si_context *sctx)
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si_pm4_set_reg(pm4, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
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}
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if (sctx->chip_class >= GFX8) {
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if (sctx->chip_class >= GFX9) {
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si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION,
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S_028B50_ACCUM_ISOLINE(40) |
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S_028B50_ACCUM_TRI(30) |
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S_028B50_ACCUM_QUAD(24) |
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S_028B50_DONUT_SPLIT(24) |
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S_028B50_TRAP_SPLIT(6));
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} else if (sctx->chip_class >= GFX8) {
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unsigned vgt_tess_distribution;
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vgt_tess_distribution =
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