diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 81a9891fbcf..d25f9cfe030 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -536,9 +536,11 @@ void si_init_shader_args(struct si_shader_context *ctx, bool ngg_cull_shader)
             declare_vs_specific_input_sgprs(ctx);
       } else {
          ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->vs_state_bits);
-         ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_offchip_layout);
-         ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tes_offchip_addr);
-         /* Declare as many input SGPRs as the VS has. */
+
+         if (ctx->stage == MESA_SHADER_TESS_EVAL) {
+            ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_offchip_layout);
+            ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tes_offchip_addr);
+         }
       }
 
       if (ctx->stage == MESA_SHADER_VERTEX)
@@ -561,19 +563,21 @@ void si_init_shader_args(struct si_shader_context *ctx, bool ngg_cull_shader)
           (ctx->stage == MESA_SHADER_VERTEX || ctx->stage == MESA_SHADER_TESS_EVAL)) {
          unsigned num_user_sgprs, num_vgprs;
 
-         if (ctx->stage == MESA_SHADER_VERTEX) {
+         if (ctx->stage == MESA_SHADER_VERTEX && ngg_cull_shader) {
             /* For the NGG cull shader, add 1 SGPR to hold
              * the vertex buffer pointer.
              */
-            num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR + ngg_cull_shader;
+            num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR + 1;
 
-            if (ngg_cull_shader && shader->selector->num_vbos_in_user_sgprs) {
-               assert(num_user_sgprs <= 8 + SI_SGPR_VS_VB_DESCRIPTOR_FIRST);
+            if (shader->selector->num_vbos_in_user_sgprs) {
+               assert(num_user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST);
                num_user_sgprs =
                   SI_SGPR_VS_VB_DESCRIPTOR_FIRST + shader->selector->num_vbos_in_user_sgprs * 4;
             }
-         } else {
+         } else if (ctx->stage == MESA_SHADER_TESS_EVAL && ngg_cull_shader) {
             num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
+         } else {
+            num_user_sgprs = SI_NUM_VS_STATE_RESOURCE_SGPRS;
          }
 
          /* The NGG cull shader has to return all 9 VGPRs.
@@ -1206,7 +1210,6 @@ static void si_dump_shader_key(const struct si_shader *shader, FILE *f)
       }
       fprintf(f, "  part.gs.prolog.tri_strip_adj_fix = %u\n",
               key->part.gs.prolog.tri_strip_adj_fix);
-      fprintf(f, "  part.gs.prolog.gfx9_prev_is_vs = %u\n", key->part.gs.prolog.gfx9_prev_is_vs);
       fprintf(f, "  as_ngg = %u\n", key->as_ngg);
       break;
 
diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h
index f503c3993bd..83dc1667ae4 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -534,7 +534,6 @@ struct si_tcs_epilog_bits {
 
 struct si_gs_prolog_bits {
    unsigned tri_strip_adj_fix : 1;
-   unsigned gfx9_prev_is_vs : 1;
 };
 
 /* Common PS bits between the shader key and the prolog key. */
diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm_gs.c b/src/gallium/drivers/radeonsi/si_shader_llvm_gs.c
index 8998b14decc..cac14686f4b 100644
--- a/src/gallium/drivers/radeonsi/si_shader_llvm_gs.c
+++ b/src/gallium/drivers/radeonsi/si_shader_llvm_gs.c
@@ -135,11 +135,7 @@ static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
       ret = si_insert_input_ptr(ctx, ret, ctx->vs_state_bits, 8 + SI_SGPR_VS_STATE_BITS);
    }
 
-   unsigned vgpr;
-   if (ctx->stage == MESA_SHADER_VERTEX)
-      vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
-   else
-      vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
+   unsigned vgpr = 8 + SI_NUM_VS_STATE_RESOURCE_SGPRS;
 
    ret = si_insert_input_ret_float(ctx, ret, ctx->gs_vtx01_offset, vgpr++);
    ret = si_insert_input_ret_float(ctx, ret, ctx->gs_vtx23_offset, vgpr++);
@@ -576,10 +572,8 @@ void si_llvm_build_gs_prolog(struct si_shader_context *ctx, union si_shader_part
    memset(&ctx->args, 0, sizeof(ctx->args));
 
    if (ctx->screen->info.chip_class >= GFX9) {
-      if (key->gs_prolog.states.gfx9_prev_is_vs)
-         num_sgprs = 8 + GFX9_VSGS_NUM_USER_SGPR;
-      else
-         num_sgprs = 8 + GFX9_TESGS_NUM_USER_SGPR;
+      /* Other user SGPRs are not needed by GS. */
+      num_sgprs = 8 + SI_NUM_VS_STATE_RESOURCE_SGPRS;
       num_vgprs = 5; /* ES inputs are not needed by GS */
    } else {
       num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index a8046027e7a..344296be09f 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1915,7 +1915,6 @@ static inline void si_shader_selector_key(struct pipe_context *ctx, struct si_sh
          } else {
             si_shader_selector_key_vs(sctx, sctx->vs_shader.cso, key, &key->part.gs.vs_prolog);
             key->part.gs.es = sctx->vs_shader.cso;
-            key->part.gs.prolog.gfx9_prev_is_vs = 1;
          }
 
          key->as_ngg = stages_key.u.ngg;