From 61c8e39649cad466c7eccfb233d6be3327142452 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Thu, 19 Aug 2021 22:09:32 +0000 Subject: [PATCH] pan/bi: Use CLPER_V6 on Mali G31 Apparently, CLPER_V7 is missing from Mali G31, but CLPER_V6 works. Fixes INSTR_INVALID_ENC faults and failures in dEQP-GLES3.functional.shaders.derivate.* on Dvalin. Technically not an errata but an implementation difference. I suspect Mali G51 will need this as well, should we ever allowlist it. Signed-off-by: Alyssa Rosenzweig Cc: mesa-stable Part-of: --- src/panfrost/bifrost/bi_quirks.h | 16 +++++++++++++--- src/panfrost/bifrost/bifrost_compile.c | 2 +- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/src/panfrost/bifrost/bi_quirks.h b/src/panfrost/bifrost/bi_quirks.h index 995dc18661b..d4e030ed537 100644 --- a/src/panfrost/bifrost/bi_quirks.h +++ b/src/panfrost/bifrost/bi_quirks.h @@ -39,15 +39,25 @@ #define BIFROST_NO_FP32_TRANSCENDENTALS (1 << 1) +/* Whether this GPU lacks support for the full form of the CLPER instruction. + * These GPUs use a simple encoding of CLPER that does not support + * inactive_result, subgroup_size, or lane_op. Using those features requires + * lowering to additional ALU instructions. The encoding forces inactive_result + * = zero, subgroup_size = subgroup4, and lane_op = none. */ + +#define BIFROST_LIMITED_CLPER (1 << 2) + static inline unsigned bifrost_get_quirks(unsigned product_id) { switch (product_id >> 8) { case 0x60: - return BIFROST_NO_PRELOAD | BIFROST_NO_FP32_TRANSCENDENTALS; + return BIFROST_NO_PRELOAD | BIFROST_NO_FP32_TRANSCENDENTALS | + BIFROST_LIMITED_CLPER; case 0x62: - return BIFROST_NO_PRELOAD; - case 0x70: + return BIFROST_NO_PRELOAD | BIFROST_LIMITED_CLPER; + case 0x70: /* G31 */ + return BIFROST_LIMITED_CLPER; case 0x71: case 0x72: case 0x73: diff --git a/src/panfrost/bifrost/bifrost_compile.c b/src/panfrost/bifrost/bifrost_compile.c index 73976566619..16c12780d49 100644 --- a/src/panfrost/bifrost/bifrost_compile.c +++ b/src/panfrost/bifrost/bifrost_compile.c @@ -1998,7 +1998,7 @@ bi_emit_alu(bi_builder *b, nir_alu_instr *instr) bi_index left, right; - if (b->shader->arch == 6) { + if (b->shader->quirks & BIFROST_LIMITED_CLPER) { left = bi_clper_v6_i32(b, s0, lane1); right = bi_clper_v6_i32(b, s0, lane2); } else {