From 619da8df77fad1d4ff83f6f05fd1a3f2e073aa13 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 18 Aug 2022 09:31:19 +0200 Subject: [PATCH] radv: move lowering FS intrinsics to radv_postprocess_nir() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Samuel Pitoiset Reviewed-By: Mike Blumenkrantz Reviewed-by: Timur Kristóf Part-of: --- src/amd/vulkan/radv_pipeline.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index d62c8bde776..184cf85f2c8 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -4312,6 +4312,10 @@ radv_postprocess_nir(struct radv_pipeline *pipeline, /* Wave and workgroup size should already be filled. */ assert(stage->info.wave_size && stage->info.workgroup_size); + if (stage->stage == MESA_SHADER_FRAGMENT) { + NIR_PASS(_, stage->nir, radv_lower_fs_intrinsics, stage, pipeline_key); + } + enum nir_lower_non_uniform_access_type lower_non_uniform_access_types = nir_lower_non_uniform_ubo_access | nir_lower_non_uniform_ssbo_access | nir_lower_non_uniform_texture_access | nir_lower_non_uniform_image_access; @@ -4669,11 +4673,6 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout radv_declare_pipeline_args(device, stages, pipeline_key); - if (stages[MESA_SHADER_FRAGMENT].nir) { - NIR_PASS(_, stages[MESA_SHADER_FRAGMENT].nir, radv_lower_fs_intrinsics, - &stages[MESA_SHADER_FRAGMENT], pipeline_key); - } - for (int i = 0; i < MESA_VULKAN_SHADER_STAGES; ++i) { if (!stages[i].nir) continue;