From 6185e4f2ff13e239b9249b8413fc94b5def1c39d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 2 Feb 2023 18:06:16 +0100 Subject: [PATCH] aco, radv: Remove VS IO information from ACO. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Timur Kristóf Reviewed-by: Rhys Perry Acked-by: Konstantin Seurer Part-of: --- .../aco_instruction_selection_setup.cpp | 42 ------------------- src/amd/compiler/aco_shader_info.h | 27 ------------ src/amd/vulkan/radv_aco_shader_info.h | 29 ------------- 3 files changed, 98 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp index 8528f3e2d3b..cb2d5e27350 100644 --- a/src/amd/compiler/aco_instruction_selection_setup.cpp +++ b/src/amd/compiler/aco_instruction_selection_setup.cpp @@ -248,25 +248,9 @@ get_reg_class(isel_context* ctx, RegType type, unsigned components, unsigned bit return RegClass::get(type, components * bitsize / 8u); } -void -setup_vs_output_info(isel_context* ctx, nir_shader* nir) -{ - const aco_vp_output_info* outinfo = &ctx->program->info.outinfo; - - ctx->export_clip_dists = outinfo->export_clip_dists; - ctx->num_clip_distances = util_bitcount(outinfo->clip_dist_mask); - ctx->num_cull_distances = util_bitcount(outinfo->cull_dist_mask); - - assert(ctx->num_clip_distances + ctx->num_cull_distances <= 8); -} - void setup_vs_variables(isel_context* ctx, nir_shader* nir) { - if (ctx->stage == vertex_vs || ctx->stage == vertex_ngg) { - setup_vs_output_info(ctx, nir); - } - if (ctx->stage == vertex_ngg) { ctx->program->config->lds_size = DIV_ROUND_UP(nir->info.shared_size, ctx->program->dev.lds_encoding_granule); @@ -282,8 +266,6 @@ setup_gs_variables(isel_context* ctx, nir_shader* nir) ctx->program->config->lds_size = ctx->program->info.gfx9_gs_ring_lds_size; /* Already in units of the alloc granularity */ } else if (ctx->stage == vertex_geometry_ngg || ctx->stage == tess_eval_geometry_ngg) { - setup_vs_output_info(ctx, nir); - ctx->program->config->lds_size = DIV_ROUND_UP(nir->info.shared_size, ctx->program->dev.lds_encoding_granule); } @@ -300,10 +282,6 @@ setup_tcs_info(isel_context* ctx, nir_shader* nir, nir_shader* vs) void setup_tes_variables(isel_context* ctx, nir_shader* nir) { - if (ctx->stage == tess_eval_vs || ctx->stage == tess_eval_ngg) { - setup_vs_output_info(ctx, nir); - } - if (ctx->stage == tess_eval_ngg) { ctx->program->config->lds_size = DIV_ROUND_UP(nir->info.shared_size, ctx->program->dev.lds_encoding_granule); @@ -315,8 +293,6 @@ setup_tes_variables(isel_context* ctx, nir_shader* nir) void setup_ms_variables(isel_context* ctx, nir_shader* nir) { - setup_vs_output_info(ctx, nir); - ctx->program->config->lds_size = DIV_ROUND_UP(nir->info.shared_size, ctx->program->dev.lds_encoding_granule); assert((ctx->program->config->lds_size * ctx->program->dev.lds_encoding_granule) < (32 * 1024)); @@ -398,24 +374,6 @@ init_context(isel_context* ctx, nir_shader* shader) ctx->ub_config.max_workgroup_size[0] = 2048; ctx->ub_config.max_workgroup_size[1] = 2048; ctx->ub_config.max_workgroup_size[2] = 2048; - for (unsigned i = 0; i < ACO_MAX_VERTEX_ATTRIBS; i++) { - pipe_format format = (pipe_format)ctx->options->key.vs.vertex_attribute_formats[i]; - const struct util_format_description* desc = util_format_description(format); - - uint32_t max; - if (desc->channel[0].type != UTIL_FORMAT_TYPE_UNSIGNED) { - max = UINT32_MAX; - } else if (desc->channel[0].normalized) { - max = 0x3f800000u; - } else { - max = 0; - for (unsigned j = 0; j < desc->nr_channels; j++) { - uint32_t chan_max = u_uintN_max(desc->channel[0].size); - max = MAX2(max, desc->channel[j].pure_integer ? chan_max : fui(chan_max)); - } - } - ctx->ub_config.vertex_attrib_max[i] = max; - } nir_divergence_analysis(shader); nir_opt_uniform_atomics(shader); diff --git a/src/amd/compiler/aco_shader_info.h b/src/amd/compiler/aco_shader_info.h index 752019af204..16650f6dddb 100644 --- a/src/amd/compiler/aco_shader_info.h +++ b/src/amd/compiler/aco_shader_info.h @@ -62,30 +62,12 @@ struct aco_vs_prolog_info { gl_shader_stage next_stage; }; -struct aco_vp_output_info { - uint8_t vs_output_param_offset[VARYING_SLOT_MAX]; - uint8_t clip_dist_mask; - uint8_t cull_dist_mask; - uint8_t param_exports; - uint8_t prim_param_exports; - bool writes_pointsize; - bool writes_layer; - bool writes_layer_per_primitive; - bool writes_viewport_index; - bool writes_viewport_index_per_primitive; - bool writes_primitive_shading_rate; - bool writes_primitive_shading_rate_per_primitive; - bool export_prim_id; - bool export_clip_dists; -}; - struct aco_shader_info { uint8_t wave_size; bool is_ngg; bool has_ngg_culling; bool has_ngg_early_prim_export; unsigned workgroup_size; - struct aco_vp_output_info outinfo; struct { bool as_es; bool as_ls; @@ -150,15 +132,6 @@ struct aco_ps_epilog_info { struct aco_stage_input { uint32_t optimisations_disabled : 1; uint32_t image_2d_view_of_3d : 1; - struct { - uint32_t instance_rate_inputs; - uint32_t instance_rate_divisors[ACO_MAX_VERTEX_ATTRIBS]; - uint8_t vertex_attribute_formats[ACO_MAX_VERTEX_ATTRIBS]; - uint32_t vertex_attribute_bindings[ACO_MAX_VERTEX_ATTRIBS]; - uint32_t vertex_attribute_offsets[ACO_MAX_VERTEX_ATTRIBS]; - uint32_t vertex_attribute_strides[ACO_MAX_VERTEX_ATTRIBS]; - uint8_t vertex_binding_align[ACO_MAX_VBS]; - } vs; struct { unsigned tess_input_vertices; diff --git a/src/amd/vulkan/radv_aco_shader_info.h b/src/amd/vulkan/radv_aco_shader_info.h index b076a96fd9f..05a77e3173d 100644 --- a/src/amd/vulkan/radv_aco_shader_info.h +++ b/src/amd/vulkan/radv_aco_shader_info.h @@ -34,27 +34,6 @@ #define ASSIGN_FIELD(x) aco_info->x = radv->x #define ASSIGN_FIELD_CP(x) memcpy(&aco_info->x, &radv->x, sizeof(radv->x)) -static inline void -radv_aco_convert_shader_vp_info(struct aco_vp_output_info *aco_info, - const struct radv_vs_output_info *radv) -{ - ASSIGN_FIELD_CP(vs_output_param_offset); - ASSIGN_FIELD(clip_dist_mask); - ASSIGN_FIELD(cull_dist_mask); - ASSIGN_FIELD(param_exports); - ASSIGN_FIELD(prim_param_exports); - ASSIGN_FIELD(writes_pointsize); - ASSIGN_FIELD(writes_layer); - ASSIGN_FIELD(writes_layer_per_primitive); - ASSIGN_FIELD(writes_viewport_index); - ASSIGN_FIELD(writes_viewport_index_per_primitive); - ASSIGN_FIELD(writes_primitive_shading_rate); - ASSIGN_FIELD(writes_primitive_shading_rate_per_primitive); - ASSIGN_FIELD(export_prim_id); - ASSIGN_FIELD(export_clip_dists); - /* don't use export params */ -} - static inline void radv_aco_convert_shader_info(struct aco_shader_info *aco_info, const struct radv_shader_info *radv, @@ -65,7 +44,6 @@ radv_aco_convert_shader_info(struct aco_shader_info *aco_info, ASSIGN_FIELD(has_ngg_culling); ASSIGN_FIELD(has_ngg_early_prim_export); ASSIGN_FIELD(workgroup_size); - radv_aco_convert_shader_vp_info(&aco_info->outinfo, &radv->outinfo); ASSIGN_FIELD(vs.as_es); ASSIGN_FIELD(vs.as_ls); ASSIGN_FIELD(vs.tcs_in_out_eq); @@ -137,13 +115,6 @@ radv_aco_convert_pipe_key(struct aco_stage_input *aco_info, const struct radv_pi radv_aco_convert_ps_epilog_key(&aco_info->ps.epilog, &radv->ps.epilog, radv_args); ASSIGN_FIELD(optimisations_disabled); ASSIGN_FIELD(image_2d_view_of_3d); - ASSIGN_FIELD(vs.instance_rate_inputs); - ASSIGN_FIELD_CP(vs.instance_rate_divisors); - ASSIGN_FIELD_CP(vs.vertex_attribute_formats); - ASSIGN_FIELD_CP(vs.vertex_attribute_bindings); - ASSIGN_FIELD_CP(vs.vertex_attribute_offsets); - ASSIGN_FIELD_CP(vs.vertex_attribute_strides); - ASSIGN_FIELD_CP(vs.vertex_binding_align); ASSIGN_FIELD(tcs.tess_input_vertices); ASSIGN_FIELD(ps.alpha_to_coverage_via_mrtz); }