From 6151eb437235c23daf3f365b1fd2c8a96cdb2524 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Thu, 6 Nov 2025 13:29:36 -0800 Subject: [PATCH] nir: Drop writemask from all Intel memory store intrinsics The backend has been fully ignoring all writemasks for a long time, so it really doesn't make sense to have them on our custom intrinsics. I'm not sure they even make sense for some of the block intrinsics. Also, the store_ssbo -> store_ssbo_intel pass was not setting writemask at all, leaving it at the default value of 0 (aka write nothing, if it had been respected...) Reviewed-by: Faith Ekstrand Reviewed-by: Lionel Landwerlin Part-of: --- src/compiler/nir/nir_intrinsics.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index 8f3c471a4d1..fc98e474202 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -2455,7 +2455,7 @@ intrinsic("resource_intel", dest_comp=1, bit_sizes=[32], # OpSubgroupBlockReadINTEL and OpSubgroupBlockWriteINTEL from SPV_INTEL_subgroups. intrinsic("load_deref_block_intel", dest_comp=0, src_comp=[-1], indices=[ACCESS], flags=[CAN_ELIMINATE]) -intrinsic("store_deref_block_intel", src_comp=[-1, 0], indices=[WRITE_MASK, ACCESS]) +intrinsic("store_deref_block_intel", src_comp=[-1, 0], indices=[ACCESS]) # Special load_ssbo intrinsic with an additional BASE value for Xe2+ offsets # src[] = { buffer_index, offset }. @@ -2463,7 +2463,7 @@ load("ssbo_intel", [-1, 1], [ACCESS, BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMIN # Special store_ssbo intrinsic with an additional BASE value for Xe2+ offsets # src[] = { value, buffer_index, offset } -store("ssbo_intel", [-1, 1], [WRITE_MASK, ACCESS, BASE, ALIGN_MUL, ALIGN_OFFSET]) +store("ssbo_intel", [-1, 1], [ACCESS, BASE, ALIGN_MUL, ALIGN_OFFSET]) # src[] = { address }. load("global_block_intel", [1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) @@ -2475,13 +2475,13 @@ load("ssbo_block_intel", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMIN load("shared_block_intel", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) # src[] = { value, address }. -store("global_block_intel", [1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) +store("global_block_intel", [1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET]) # src[] = { value, block_index, offset } -store("ssbo_block_intel", [-1, 1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) +store("ssbo_block_intel", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET]) # src[] = { value, offset }. -store("shared_block_intel", [1], [BASE, WRITE_MASK, ALIGN_MUL, ALIGN_OFFSET]) +store("shared_block_intel", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET]) # src[] = { address }. load("global_constant_uniform_block_intel", [1],