From 6095b70f857f0bd6d01db4c979e73f21aecc4f00 Mon Sep 17 00:00:00 2001 From: Konstantin Seurer Date: Thu, 8 Feb 2024 16:50:08 +0100 Subject: [PATCH] radv/rt: Use 32-bit offsets for load_sbt_entry Totals from 82 (18.06% of 454) affected shaders: MaxWaves: 820 -> 821 (+0.12%) Instrs: 2765694 -> 2766338 (+0.02%); split: -0.08%, +0.10% CodeSize: 14751988 -> 14735464 (-0.11%); split: -0.13%, +0.01% VGPRs: 8464 -> 8448 (-0.19%) SpillSGPRs: 454 -> 512 (+12.78%) Latency: 19368679 -> 19344967 (-0.12%); split: -0.21%, +0.09% InvThroughput: 5354427 -> 5346317 (-0.15%); split: -0.24%, +0.08% VClause: 100183 -> 100331 (+0.15%); split: -0.02%, +0.17% SClause: 66584 -> 66590 (+0.01%); split: -0.02%, +0.03% Copies: 237008 -> 238684 (+0.71%); split: -0.53%, +1.23% Branches: 113344 -> 113386 (+0.04%); split: -0.00%, +0.04% PreSGPRs: 6141 -> 6194 (+0.86%) PreVGPRs: 7916 -> 7880 (-0.45%) Reviewed-by: Friedrich Vock Part-of: --- src/amd/vulkan/nir/radv_nir_rt_shader.c | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/src/amd/vulkan/nir/radv_nir_rt_shader.c b/src/amd/vulkan/nir/radv_nir_rt_shader.c index d20f4092a5d..f21cbfb5091 100644 --- a/src/amd/vulkan/nir/radv_nir_rt_shader.c +++ b/src/amd/vulkan/nir/radv_nir_rt_shader.c @@ -359,33 +359,26 @@ enum sbt_entry { SBT_ANY_HIT_IDX = offsetof(struct radv_pipeline_group_handle, any_hit_index), }; -static nir_def * -get_sbt_ptr(nir_builder *b, nir_def *idx, enum sbt_type binding) +static void +load_sbt_entry(nir_builder *b, const struct rt_variables *vars, nir_def *idx, enum sbt_type binding, + enum sbt_entry offset) { nir_def *desc_base_addr = nir_load_sbt_base_amd(b); nir_def *desc = nir_pack_64_2x32(b, nir_load_smem_amd(b, 2, desc_base_addr, nir_imm_int(b, binding))); nir_def *stride_offset = nir_imm_int(b, binding + (binding == SBT_RAYGEN ? 8 : 16)); - nir_def *stride = nir_pack_64_2x32(b, nir_load_smem_amd(b, 2, desc_base_addr, stride_offset)); + nir_def *stride = nir_load_smem_amd(b, 1, desc_base_addr, stride_offset); - return nir_iadd(b, desc, nir_imul(b, nir_u2u64(b, idx), stride)); -} - -static void -load_sbt_entry(nir_builder *b, const struct rt_variables *vars, nir_def *idx, enum sbt_type binding, - enum sbt_entry offset) -{ - nir_def *addr = get_sbt_ptr(b, idx, binding); - nir_def *load_addr = nir_iadd_imm(b, addr, offset); + nir_def *addr = nir_iadd(b, desc, nir_u2u64(b, nir_iadd_imm(b, nir_imul(b, idx, stride), offset))); if (offset == SBT_RECURSIVE_PTR) { - nir_store_var(b, vars->shader_addr, nir_build_load_global(b, 1, 64, load_addr), 1); + nir_store_var(b, vars->shader_addr, nir_build_load_global(b, 1, 64, addr), 1); } else { - nir_store_var(b, vars->idx, nir_build_load_global(b, 1, 32, load_addr), 1); + nir_store_var(b, vars->idx, nir_build_load_global(b, 1, 32, addr), 1); } - nir_def *record_addr = nir_iadd_imm(b, addr, RADV_RT_HANDLE_SIZE); + nir_def *record_addr = nir_iadd_imm(b, addr, RADV_RT_HANDLE_SIZE - offset); nir_store_var(b, vars->shader_record_ptr, record_addr, 1); }