From 5fead24365d329d03a1db5ad7a3f546a49bbcab1 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Tue, 1 Aug 2023 11:17:24 -0400 Subject: [PATCH] treewide: Drop is_ssa asserts We only see SSA now. Via Coccinelle patch: @@ expression x; @@ -assert(x.is_ssa); Signed-off-by: Alyssa Rosenzweig Acked-by: Faith Ekstrand Part-of: --- src/amd/llvm/ac_nir_to_llvm.c | 3 --- .../compiler/v3d_nir_lower_image_load_store.c | 1 - src/broadcom/compiler/v3d_nir_lower_line_smooth.c | 2 -- src/compiler/glsl/gl_nir_lower_atomics.c | 1 - src/compiler/glsl/gl_nir_lower_buffers.c | 3 --- src/compiler/glsl/gl_nir_lower_samplers_as_deref.c | 3 --- src/compiler/nir/nir_clone.c | 1 - src/compiler/nir/nir_from_ssa.c | 5 ----- src/compiler/nir/nir_instr_set.c | 5 ----- src/compiler/nir/nir_legacy.c | 2 -- src/compiler/nir/nir_liveness.c | 1 - src/compiler/nir/nir_loop_analyze.c | 4 ---- src/compiler/nir/nir_lower_alu.c | 2 -- src/compiler/nir/nir_lower_alu_width.c | 3 --- src/compiler/nir/nir_lower_array_deref_of_vec.c | 1 - src/compiler/nir/nir_lower_bit_size.c | 3 --- src/compiler/nir/nir_lower_blend.c | 1 - src/compiler/nir/nir_lower_bool_to_bitsize.c | 1 - src/compiler/nir/nir_lower_bool_to_int32.c | 2 -- src/compiler/nir/nir_lower_cl_images.c | 2 -- src/compiler/nir/nir_lower_clip.c | 1 - src/compiler/nir/nir_lower_double_ops.c | 4 ---- src/compiler/nir/nir_lower_drawpixels.c | 2 -- src/compiler/nir/nir_lower_fragcolor.c | 1 - src/compiler/nir/nir_lower_goto_ifs.c | 1 - src/compiler/nir/nir_lower_helper_writes.c | 1 - src/compiler/nir/nir_lower_indirect_derefs.c | 1 - src/compiler/nir/nir_lower_int64.c | 14 -------------- src/compiler/nir/nir_lower_interpolation.c | 4 ---- src/compiler/nir/nir_lower_io.c | 10 ---------- src/compiler/nir/nir_lower_io_to_scalar.c | 6 ------ src/compiler/nir/nir_lower_io_to_vector.c | 1 - src/compiler/nir/nir_lower_mem_access_bit_sizes.c | 3 --- src/compiler/nir/nir_lower_memcpy.c | 1 - src/compiler/nir/nir_lower_multiview.c | 1 - src/compiler/nir/nir_lower_non_uniform_access.c | 1 - src/compiler/nir/nir_lower_point_size.c | 1 - src/compiler/nir/nir_lower_point_smooth.c | 1 - src/compiler/nir/nir_lower_poly_line_smooth.c | 1 - .../nir/nir_lower_readonly_images_to_tex.c | 3 --- src/compiler/nir/nir_lower_samplers.c | 1 - src/compiler/nir/nir_lower_shader_calls.c | 1 - src/compiler/nir/nir_lower_single_sampled.c | 1 - src/compiler/nir/nir_lower_subgroups.c | 11 ----------- src/compiler/nir/nir_lower_system_values.c | 2 -- src/compiler/nir/nir_lower_tex.c | 11 ----------- src/compiler/nir/nir_lower_two_sided_color.c | 1 - src/compiler/nir/nir_lower_vars_to_ssa.c | 3 --- src/compiler/nir/nir_lower_vec3_to_vec4.c | 2 -- src/compiler/nir/nir_lower_vec_to_regs.c | 4 ---- src/compiler/nir/nir_lower_wpos_center.c | 2 -- src/compiler/nir/nir_lower_wpos_ytransform.c | 1 - src/compiler/nir/nir_opt_combine_stores.c | 1 - src/compiler/nir/nir_opt_conditional_discard.c | 2 -- src/compiler/nir/nir_opt_dead_cf.c | 2 -- src/compiler/nir/nir_opt_idiv_const.c | 1 - src/compiler/nir/nir_opt_if.c | 2 -- src/compiler/nir/nir_opt_intrinsics.c | 3 --- src/compiler/nir/nir_opt_peephole_select.c | 1 - src/compiler/nir/nir_opt_phi_precision.c | 12 ------------ src/compiler/nir/nir_opt_remove_phis.c | 3 --- src/compiler/nir/nir_opt_undef.c | 4 ---- src/compiler/nir/nir_print.c | 1 - src/compiler/nir/nir_range_analysis.c | 1 - src/compiler/nir/nir_schedule.c | 6 ------ src/compiler/nir/nir_search.c | 13 ------------- src/compiler/nir/nir_serialize.c | 5 ----- src/compiler/nir/nir_split_vars.c | 3 --- src/compiler/nir/tests/vars_tests.cpp | 1 - src/freedreno/ir3/ir3_nir_lower_io_offsets.c | 3 --- src/freedreno/ir3/ir3_nir_lower_tex_prefetch.c | 1 - src/freedreno/ir3/ir3_nir_move_varying_inputs.c | 2 -- src/freedreno/vulkan/tu_nir_lower_multiview.cc | 1 - src/gallium/auxiliary/gallivm/lp_bld_nir.c | 3 --- src/gallium/auxiliary/nir/nir_to_tgsi.c | 2 -- src/gallium/drivers/crocus/crocus_program.c | 2 -- src/gallium/drivers/d3d12/d3d12_nir_passes.c | 1 - src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c | 1 - src/gallium/drivers/freedreno/a2xx/ir2_nir.c | 1 - src/gallium/drivers/iris/iris_program.c | 2 -- src/gallium/drivers/lima/ir/gp/nir.c | 2 -- src/gallium/drivers/lima/ir/lima_nir_split_loads.c | 3 --- src/gallium/drivers/lima/ir/pp/nir.c | 2 -- src/gallium/drivers/r600/sfn/sfn_nir.cpp | 1 - .../drivers/r600/sfn/sfn_nir_lower_64bit.cpp | 1 - .../drivers/r600/sfn/sfn_nir_lower_tess_io.cpp | 2 -- .../drivers/r600/sfn/sfn_nir_vectorize_vs_inputs.c | 2 -- src/gallium/drivers/r600/sfn/sfn_valuefactory.cpp | 4 ---- src/gallium/drivers/vc4/vc4_nir_lower_txf_ms.c | 2 -- src/gallium/drivers/vc4/vc4_program.c | 3 --- .../drivers/zink/nir_to_spirv/nir_to_spirv.c | 2 -- src/gallium/drivers/zink/zink_compiler.c | 4 ---- src/gallium/frontends/rusticl/rusticl_nir.c | 2 -- src/imagination/rogue/nir/rogue_nir_lower_io.c | 1 - src/intel/compiler/brw_fs_nir.cpp | 12 ------------ src/intel/compiler/brw_nir.c | 6 ------ src/intel/compiler/brw_nir_lower_conversions.c | 1 - .../compiler/brw_nir_lower_shading_rate_output.c | 1 - src/intel/compiler/brw_nir_opt_peephole_ffma.c | 4 ---- src/intel/compiler/brw_nir_rt.c | 3 --- src/intel/compiler/brw_vec4_nir.cpp | 2 -- src/intel/vulkan/anv_mesh_perprim_wa.c | 3 --- src/intel/vulkan/anv_nir_apply_pipeline_layout.c | 11 ----------- src/intel/vulkan/anv_nir_lower_multiview.c | 2 -- .../vulkan_hasvk/anv_nir_apply_pipeline_layout.c | 10 ---------- src/intel/vulkan_hasvk/anv_nir_lower_multiview.c | 2 -- .../vulkan_hasvk/anv_nir_lower_ycbcr_textures.c | 1 - src/mesa/state_tracker/st_nir_lower_builtin.c | 1 - src/microsoft/compiler/dxil_nir.c | 12 ------------ src/microsoft/compiler/dxil_nir_tess.c | 1 - src/microsoft/compiler/nir_to_dxil.c | 6 ------ src/nouveau/codegen/nv50_ir_from_nir.cpp | 3 --- .../compiler/bi_lower_divergent_indirects.c | 1 - src/panfrost/midgard/midgard_compile.c | 2 -- src/panfrost/midgard/midgard_nir_type_csel.c | 1 - src/panfrost/util/pan_lower_64bit_intrin.c | 1 - .../vulkan/panvk_vX_nir_lower_descriptors.c | 6 ------ src/vulkan/runtime/vk_nir_convert_ycbcr.c | 1 - 118 files changed, 348 deletions(-) diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 5233e469563..46cfbfef414 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -52,7 +52,6 @@ static LLVMTypeRef get_def_type(struct ac_nir_context *ctx, const nir_ssa_def *d static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src) { - assert(src.is_ssa); return nir->ssa_defs[src.ssa->index]; } @@ -1477,8 +1476,6 @@ static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx, const nir_te if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) { unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa); - assert(instr->dest.is_ssa); - /* Buffers don't support A16. */ if (args->a16) args->coords[0] = LLVMBuildZExt(ctx->ac.builder, args->coords[0], ctx->ac.i32, ""); diff --git a/src/broadcom/compiler/v3d_nir_lower_image_load_store.c b/src/broadcom/compiler/v3d_nir_lower_image_load_store.c index 2900a29817f..b4cbfa7c588 100644 --- a/src/broadcom/compiler/v3d_nir_lower_image_load_store.c +++ b/src/broadcom/compiler/v3d_nir_lower_image_load_store.c @@ -182,7 +182,6 @@ v3d_nir_lower_image_load(nir_builder *b, nir_intrinsic_instr *instr) b->cursor = nir_after_instr(&instr->instr); - assert(instr->dest.is_ssa); nir_ssa_def *result = &instr->dest.ssa; if (util_format_is_pure_uint(format)) { result = nir_format_unpack_uint(b, result, bits16, 4); diff --git a/src/broadcom/compiler/v3d_nir_lower_line_smooth.c b/src/broadcom/compiler/v3d_nir_lower_line_smooth.c index 750ee4d32cd..f6f27a1193b 100644 --- a/src/broadcom/compiler/v3d_nir_lower_line_smooth.c +++ b/src/broadcom/compiler/v3d_nir_lower_line_smooth.c @@ -75,8 +75,6 @@ lower_line_smooth_func(struct lower_line_smooth_state *state, intr->num_components != 4) continue; - assert(intr->src[0].is_ssa); - lower_line_smooth_intrinsic(state, &b, intr); progress = true; } diff --git a/src/compiler/glsl/gl_nir_lower_atomics.c b/src/compiler/glsl/gl_nir_lower_atomics.c index 69bdea71ba0..e39889e778f 100644 --- a/src/compiler/glsl/gl_nir_lower_atomics.c +++ b/src/compiler/glsl/gl_nir_lower_atomics.c @@ -122,7 +122,6 @@ lower_deref_instr(nir_builder *b, nir_intrinsic_instr *instr, for (nir_deref_instr *d = deref; d->deref_type != nir_deref_type_var; d = nir_deref_instr_parent(d)) { assert(d->deref_type == nir_deref_type_array); - assert(d->arr.index.is_ssa); unsigned array_stride = ATOMIC_COUNTER_SIZE; if (glsl_type_is_array(d->type)) diff --git a/src/compiler/glsl/gl_nir_lower_buffers.c b/src/compiler/glsl/gl_nir_lower_buffers.c index 2855e2f2c15..1a1d623a03b 100644 --- a/src/compiler/glsl/gl_nir_lower_buffers.c +++ b/src/compiler/glsl/gl_nir_lower_buffers.c @@ -194,7 +194,6 @@ lower_buffer_interface_derefs_impl(nir_function_impl *impl, break; /* We use nir_address_format_32bit_index_offset */ - assert(deref->dest.is_ssa); assert(deref->dest.ssa.bit_size == 32); deref->dest.ssa.num_components = 2; @@ -261,7 +260,6 @@ lower_buffer_interface_derefs_impl(nir_function_impl *impl, * from the SSBO. */ if (glsl_type_is_boolean(deref->type)) { - assert(intrin->dest.is_ssa); b.cursor = nir_after_instr(&intrin->instr); intrin->dest.ssa.bit_size = 32; nir_ssa_def *bval = nir_i2b(&b, &intrin->dest.ssa); @@ -289,7 +287,6 @@ lower_buffer_interface_derefs_impl(nir_function_impl *impl, * step but in practice it doesn't cost much. */ if (glsl_type_is_boolean(deref->type)) { - assert(intrin->src[1].is_ssa); b.cursor = nir_before_instr(&intrin->instr); nir_ssa_def *ival = nir_b2i32(&b, intrin->src[1].ssa); nir_instr_rewrite_src(&intrin->instr, &intrin->src[1], diff --git a/src/compiler/glsl/gl_nir_lower_samplers_as_deref.c b/src/compiler/glsl/gl_nir_lower_samplers_as_deref.c index 53e89ad900d..03dc81b1f13 100644 --- a/src/compiler/glsl/gl_nir_lower_samplers_as_deref.c +++ b/src/compiler/glsl/gl_nir_lower_samplers_as_deref.c @@ -281,8 +281,6 @@ lower_sampler(nir_tex_instr *instr, struct lower_samplers_as_deref_state *state, b->cursor = nir_before_instr(&instr->instr); if (texture_idx >= 0) { - assert(instr->src[texture_idx].src.is_ssa); - nir_deref_instr *texture_deref = lower_deref(b, state, nir_src_as_deref(instr->src[texture_idx].src)); /* only lower non-bindless: */ @@ -294,7 +292,6 @@ lower_sampler(nir_tex_instr *instr, struct lower_samplers_as_deref_state *state, } if (sampler_idx >= 0) { - assert(instr->src[sampler_idx].src.is_ssa); nir_deref_instr *sampler_deref = lower_deref(b, state, nir_src_as_deref(instr->src[sampler_idx].src)); /* only lower non-bindless: */ diff --git a/src/compiler/nir/nir_clone.c b/src/compiler/nir/nir_clone.c index ffbae1863ba..7eb217096f9 100644 --- a/src/compiler/nir/nir_clone.c +++ b/src/compiler/nir/nir_clone.c @@ -587,7 +587,6 @@ fixup_phi_srcs(clone_state *state) /* Remove from this list */ list_del(&src->src.use_link); - assert(src->src.is_ssa); src->src.ssa = remap_local(state, src->src.ssa); list_addtail(&src->src.use_link, &src->src.ssa->uses); diff --git a/src/compiler/nir/nir_from_ssa.c b/src/compiler/nir/nir_from_ssa.c index e877205a2f3..ee8c1711d97 100644 --- a/src/compiler/nir/nir_from_ssa.c +++ b/src/compiler/nir/nir_from_ssa.c @@ -441,11 +441,9 @@ static bool coalesce_phi_nodes_block(nir_block *block, struct from_ssa_state *state) { nir_foreach_phi(phi, block) { - assert(phi->dest.is_ssa); merge_node *dest_node = get_merge_node(&phi->dest.ssa, state); nir_foreach_phi_src(src, phi) { - assert(src->src.is_ssa); if (nir_src_is_undef(src->src)) continue; @@ -464,9 +462,7 @@ aggressive_coalesce_parallel_copy(nir_parallel_copy_instr *pcopy, { nir_foreach_parallel_copy_entry(entry, pcopy) { assert(!entry->src_is_reg); - assert(entry->src.is_ssa); assert(!entry->dest_is_reg); - assert(entry->dest.dest.is_ssa); assert(entry->dest.dest.ssa.num_components == entry->src.ssa->num_components); @@ -625,7 +621,6 @@ remove_no_op_phi(nir_instr *instr, struct from_ssa_state *state) #ifndef NDEBUG nir_phi_instr *phi = nir_instr_as_phi(instr); - assert(phi->dest.is_ssa); struct hash_entry *entry = _mesa_hash_table_search(state->merge_node_table, &phi->dest.ssa); assert(entry != NULL); diff --git a/src/compiler/nir/nir_instr_set.c b/src/compiler/nir/nir_instr_set.c index 040985b3a84..4d493be9aba 100644 --- a/src/compiler/nir/nir_instr_set.c +++ b/src/compiler/nir/nir_instr_set.c @@ -767,21 +767,16 @@ nir_instr_get_dest_ssa_def(nir_instr *instr) { switch (instr->type) { case nir_instr_type_alu: - assert(nir_instr_as_alu(instr)->dest.dest.is_ssa); return &nir_instr_as_alu(instr)->dest.dest.ssa; case nir_instr_type_deref: - assert(nir_instr_as_deref(instr)->dest.is_ssa); return &nir_instr_as_deref(instr)->dest.ssa; case nir_instr_type_load_const: return &nir_instr_as_load_const(instr)->def; case nir_instr_type_phi: - assert(nir_instr_as_phi(instr)->dest.is_ssa); return &nir_instr_as_phi(instr)->dest.ssa; case nir_instr_type_intrinsic: - assert(nir_instr_as_intrinsic(instr)->dest.is_ssa); return &nir_instr_as_intrinsic(instr)->dest.ssa; case nir_instr_type_tex: - assert(nir_instr_as_tex(instr)->dest.is_ssa); return &nir_instr_as_tex(instr)->dest.ssa; default: unreachable("We never ask for any of these"); diff --git a/src/compiler/nir/nir_legacy.c b/src/compiler/nir/nir_legacy.c index 25e11e9eb9b..593d7fdbcdc 100644 --- a/src/compiler/nir/nir_legacy.c +++ b/src/compiler/nir/nir_legacy.c @@ -12,7 +12,6 @@ bool nir_legacy_float_mod_folds(nir_alu_instr *mod) { assert(mod->op == nir_op_fabs || mod->op == nir_op_fneg); - assert(mod->dest.dest.is_ssa); /* No legacy user supports fp64 modifiers */ if (mod->dest.dest.ssa.bit_size == 64) @@ -223,7 +222,6 @@ chase_fsat(nir_ssa_def **def) /* Otherwise, we're good */ nir_alu_instr *alu = nir_instr_as_alu(use->parent_instr); - assert(alu->dest.dest.is_ssa); *def = &alu->dest.dest.ssa; return true; } diff --git a/src/compiler/nir/nir_liveness.c b/src/compiler/nir/nir_liveness.c index ce5fe18f6cb..2d53e7c8acd 100644 --- a/src/compiler/nir/nir_liveness.c +++ b/src/compiler/nir/nir_liveness.c @@ -109,7 +109,6 @@ propagate_across_edge(nir_block *pred, nir_block *succ, memcpy(live, succ->live_in, state->bitset_words * sizeof *live); nir_foreach_phi(phi, succ) { - assert(phi->dest.is_ssa); set_ssa_def_dead(&phi->dest.ssa, live); } diff --git a/src/compiler/nir/nir_loop_analyze.c b/src/compiler/nir/nir_loop_analyze.c index 8651b46a40c..9b7bdd41434 100644 --- a/src/compiler/nir/nir_loop_analyze.c +++ b/src/compiler/nir/nir_loop_analyze.c @@ -336,7 +336,6 @@ phi_instr_as_alu(nir_phi_instr *phi) { nir_alu_instr *first = NULL; nir_foreach_phi_src(src, phi) { - assert(src->src.is_ssa); if (src->src.ssa->parent_instr->type != nir_instr_type_alu) return NULL; @@ -356,7 +355,6 @@ static bool alu_src_has_identity_swizzle(nir_alu_instr *alu, unsigned src_idx) { assert(nir_op_infos[alu->op].input_sizes[src_idx] == 0); - assert(alu->dest.dest.is_ssa); for (unsigned i = 0; i < alu->dest.dest.ssa.num_components; i++) { if (alu->src[src_idx].swizzle[i] != i) return false; @@ -599,7 +597,6 @@ find_array_access_via_induction(loop_info_state *state, if (d->deref_type != nir_deref_type_array) continue; - assert(d->arr.index.is_ssa); nir_loop_variable *array_index = get_loop_var(d->arr.index.ssa, state); if (array_index->type != basic_induction) @@ -1237,7 +1234,6 @@ find_trip_count(loop_info_state *state, unsigned execution_mode, list_for_each_entry(nir_loop_terminator, terminator, &state->loop->info->loop_terminator_list, loop_terminator_link) { - assert(terminator->nif->condition.is_ssa); nir_ssa_scalar cond = { terminator->nif->condition.ssa, 0 }; if (!nir_ssa_scalar_is_alu(cond)) { diff --git a/src/compiler/nir/nir_lower_alu.c b/src/compiler/nir/nir_lower_alu.c index 8051ee71431..03852d5496a 100644 --- a/src/compiler/nir/nir_lower_alu.c +++ b/src/compiler/nir/nir_lower_alu.c @@ -49,8 +49,6 @@ lower_alu_instr(nir_builder *b, nir_instr *instr_, UNUSED void *cb_data) nir_ssa_def *lowered = NULL; - assert(instr->dest.dest.is_ssa); - b->cursor = nir_before_instr(&instr->instr); b->exact = instr->exact; diff --git a/src/compiler/nir/nir_lower_alu_width.c b/src/compiler/nir/nir_lower_alu_width.c index f2872f0a87b..9ba2b818d78 100644 --- a/src/compiler/nir/nir_lower_alu_width.c +++ b/src/compiler/nir/nir_lower_alu_width.c @@ -51,8 +51,6 @@ inst_is_vector_alu(const nir_instr *instr, const void *_state) /* There is no ALU instruction which has a scalar destination, scalar * src[0], and some other vector source. */ - assert(alu->dest.dest.is_ssa); - assert(alu->src[0].src.is_ssa); return alu->dest.dest.ssa.num_components > 1 || nir_op_infos[alu->op].input_sizes[0] > 1; } @@ -189,7 +187,6 @@ lower_alu_instr_width(nir_builder *b, nir_instr *instr, void *_data) unsigned num_src = nir_op_infos[alu->op].num_inputs; unsigned i, chan; - assert(alu->dest.dest.is_ssa); assert(alu->dest.write_mask != 0); b->exact = alu->exact; diff --git a/src/compiler/nir/nir_lower_array_deref_of_vec.c b/src/compiler/nir/nir_lower_array_deref_of_vec.c index 5b0d151d479..2587cd9c7be 100644 --- a/src/compiler/nir/nir_lower_array_deref_of_vec.c +++ b/src/compiler/nir/nir_lower_array_deref_of_vec.c @@ -106,7 +106,6 @@ nir_lower_array_deref_of_vec_impl(nir_function_impl *impl, b.cursor = nir_after_instr(&intrin->instr); if (intrin->intrinsic == nir_intrinsic_store_deref) { - assert(intrin->src[1].is_ssa); nir_ssa_def *value = intrin->src[1].ssa; if (nir_src_is_const(deref->arr.index)) { diff --git a/src/compiler/nir/nir_lower_bit_size.c b/src/compiler/nir/nir_lower_bit_size.c index 1520baeaf9e..45ba46367c8 100644 --- a/src/compiler/nir/nir_lower_bit_size.c +++ b/src/compiler/nir/nir_lower_bit_size.c @@ -219,13 +219,11 @@ static void lower_phi_instr(nir_builder *b, nir_phi_instr *phi, unsigned bit_size, nir_phi_instr *last_phi) { - assert(phi->dest.is_ssa); unsigned old_bit_size = phi->dest.ssa.bit_size; assert(old_bit_size < bit_size); nir_foreach_phi_src(src, phi) { b->cursor = nir_after_block_before_jump(src->pred); - assert(src->src.is_ssa); nir_ssa_def *new_src = nir_u2uN(b, src->src.ssa, bit_size); nir_instr_rewrite_src(&phi->instr, &src->src, nir_src_for_ssa(new_src)); @@ -347,7 +345,6 @@ lower_64bit_phi_instr(nir_builder *b, nir_instr *instr, UNUSED void *cb_data) return false; nir_phi_instr *phi = nir_instr_as_phi(instr); - assert(phi->dest.is_ssa); if (phi->dest.ssa.bit_size <= 32) return false; diff --git a/src/compiler/nir/nir_lower_blend.c b/src/compiler/nir/nir_lower_blend.c index e050a60e1ca..6ea02341273 100644 --- a/src/compiler/nir/nir_lower_blend.c +++ b/src/compiler/nir/nir_lower_blend.c @@ -541,7 +541,6 @@ nir_lower_blend_instr(nir_builder *b, nir_instr *instr, void *data) /* Grab the input color. We always want 4 channels during blend. Dead * code will clean up any channels we don't need. */ - assert(store->src[0].is_ssa); nir_ssa_def *src = nir_pad_vector(b, store->src[0].ssa, 4); assert(nir_src_as_uint(store->src[1]) == 0 && "store_output invariant"); diff --git a/src/compiler/nir/nir_lower_bool_to_bitsize.c b/src/compiler/nir/nir_lower_bool_to_bitsize.c index ebc1fb03202..a176a74bff7 100644 --- a/src/compiler/nir/nir_lower_bool_to_bitsize.c +++ b/src/compiler/nir/nir_lower_bool_to_bitsize.c @@ -364,7 +364,6 @@ lower_phi_instr(nir_builder *b, nir_phi_instr *phi) if (dst_bit_size == 0) { dst_bit_size = src_bit_size; } else if (src_bit_size != dst_bit_size) { - assert(phi_src->src.is_ssa); b->cursor = nir_before_src(&phi_src->src); nir_op convert_op = get_bool_convert_opcode(dst_bit_size); nir_ssa_def *new_src = diff --git a/src/compiler/nir/nir_lower_bool_to_int32.c b/src/compiler/nir/nir_lower_bool_to_int32.c index 3febb73e15f..f9e288458bb 100644 --- a/src/compiler/nir/nir_lower_bool_to_int32.c +++ b/src/compiler/nir/nir_lower_bool_to_int32.c @@ -47,8 +47,6 @@ lower_alu_instr(nir_alu_instr *alu) { const nir_op_info *op_info = &nir_op_infos[alu->op]; - assert(alu->dest.dest.is_ssa); - switch (alu->op) { case nir_op_mov: case nir_op_vec2: diff --git a/src/compiler/nir/nir_lower_cl_images.c b/src/compiler/nir/nir_lower_cl_images.c index 5806b101982..a15ceb22572 100644 --- a/src/compiler/nir/nir_lower_cl_images.c +++ b/src/compiler/nir/nir_lower_cl_images.c @@ -215,7 +215,6 @@ nir_lower_cl_images(nir_shader *shader, bool lower_image_derefs, bool lower_samp NIR_SRC_INIT); continue; } else { - assert(tex->src[i].src.is_ssa); b.cursor = nir_before_instr(&tex->instr); /* Back-ends expect a 32-bit thing, not 64-bit */ nir_ssa_def *offset = nir_u2u32(&b, tex->src[i].src.ssa); @@ -254,7 +253,6 @@ nir_lower_cl_images(nir_shader *shader, bool lower_image_derefs, bool lower_samp if (!lower_image_derefs) break; - assert(intrin->src[0].is_ssa); b.cursor = nir_before_instr(&intrin->instr); /* Back-ends expect a 32-bit thing, not 64-bit */ nir_ssa_def *offset = nir_u2u32(&b, intrin->src[0].ssa); diff --git a/src/compiler/nir/nir_lower_clip.c b/src/compiler/nir/nir_lower_clip.c index 80fc5ad1950..6bd69e619d5 100644 --- a/src/compiler/nir/nir_lower_clip.c +++ b/src/compiler/nir/nir_lower_clip.c @@ -151,7 +151,6 @@ find_output_in_block(nir_block *block, unsigned drvloc) nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); if ((intr->intrinsic == nir_intrinsic_store_output) && nir_intrinsic_base(intr) == drvloc) { - assert(intr->src[0].is_ssa); assert(nir_src_is_const(intr->src[1])); return intr->src[0].ssa; } diff --git a/src/compiler/nir/nir_lower_double_ops.c b/src/compiler/nir/nir_lower_double_ops.c index 1d106ddf414..b890ef55ca7 100644 --- a/src/compiler/nir/nir_lower_double_ops.c +++ b/src/compiler/nir/nir_lower_double_ops.c @@ -461,9 +461,6 @@ lower_doubles_instr_to_soft(nir_builder *b, nir_alu_instr *instr, if (!(options & nir_lower_fp64_full_software)) return NULL; - - assert(instr->dest.dest.is_ssa); - const char *name; const char *mangled_name; const struct glsl_type *return_type = glsl_uint64_t_type(); @@ -673,7 +670,6 @@ should_lower_double_instr(const nir_instr *instr, const void *_data) const nir_alu_instr *alu = nir_instr_as_alu(instr); - assert(alu->dest.dest.is_ssa); bool is_64 = alu->dest.dest.ssa.bit_size == 64; unsigned num_srcs = nir_op_infos[alu->op].num_inputs; diff --git a/src/compiler/nir/nir_lower_drawpixels.c b/src/compiler/nir/nir_lower_drawpixels.c index 796d7586b3f..52a904936f8 100644 --- a/src/compiler/nir/nir_lower_drawpixels.c +++ b/src/compiler/nir/nir_lower_drawpixels.c @@ -85,8 +85,6 @@ lower_color(nir_builder *b, lower_drawpixels_state *state, nir_intrinsic_instr * nir_tex_instr *tex; nir_ssa_def *def; - assert(intr->dest.is_ssa); - b->cursor = nir_before_instr(&intr->instr); texcoord = get_texcoord(b, state); diff --git a/src/compiler/nir/nir_lower_fragcolor.c b/src/compiler/nir/nir_lower_fragcolor.c index d9c3e051729..7bd4a3e8033 100644 --- a/src/compiler/nir/nir_lower_fragcolor.c +++ b/src/compiler/nir/nir_lower_fragcolor.c @@ -65,7 +65,6 @@ lower_fragcolor_instr(nir_builder *b, nir_instr *intr, void *data) return false; b->cursor = nir_after_instr(&instr->instr); - assert(instr->src[1].is_ssa); nir_ssa_def *frag_color = instr->src[1].ssa; ralloc_free(out->name); diff --git a/src/compiler/nir/nir_lower_goto_ifs.c b/src/compiler/nir/nir_lower_goto_ifs.c index 038c3161c57..10e5f01742e 100644 --- a/src/compiler/nir/nir_lower_goto_ifs.c +++ b/src/compiler/nir/nir_lower_goto_ifs.c @@ -176,7 +176,6 @@ set_path_vars_cond(nir_builder *b, struct path_fork *fork, nir_src condition, break; } else { - assert(condition.is_ssa); nir_ssa_def *ssa_def = condition.ssa; assert(ssa_def->bit_size == 1); assert(ssa_def->num_components == 1); diff --git a/src/compiler/nir/nir_lower_helper_writes.c b/src/compiler/nir/nir_lower_helper_writes.c index 49ffedc4234..a0f6b017197 100644 --- a/src/compiler/nir/nir_lower_helper_writes.c +++ b/src/compiler/nir/nir_lower_helper_writes.c @@ -83,7 +83,6 @@ lower(nir_builder *b, nir_instr *instr, void *data) nir_pop_if(b, NULL); if (has_dest) { - assert(intr->dest.is_ssa); nir_ssa_def *phi = nir_if_phi(b, &intr->dest.ssa, undef); /* We can't use nir_ssa_def_rewrite_uses_after on phis, so use the global diff --git a/src/compiler/nir/nir_lower_indirect_derefs.c b/src/compiler/nir/nir_lower_indirect_derefs.c index 8057d3ac033..1c0a44482ae 100644 --- a/src/compiler/nir/nir_lower_indirect_derefs.c +++ b/src/compiler/nir/nir_lower_indirect_derefs.c @@ -169,7 +169,6 @@ lower_indirect_derefs_block(nir_block *block, nir_builder *b, assert(path.path[0] == base); if (intrin->intrinsic == nir_intrinsic_store_deref) { - assert(intrin->src[1].is_ssa); emit_load_store_deref(b, intrin, base, &path.path[1], NULL, intrin->src[1].ssa); } else { diff --git a/src/compiler/nir/nir_lower_int64.c b/src/compiler/nir/nir_lower_int64.c index 5a582e73032..d6818bc22f6 100644 --- a/src/compiler/nir/nir_lower_int64.c +++ b/src/compiler/nir/nir_lower_int64.c @@ -1082,13 +1082,10 @@ should_lower_int64_alu_instr(const nir_alu_instr *alu, case nir_op_u2u8: case nir_op_u2u16: case nir_op_u2u32: - assert(alu->src[0].src.is_ssa); if (alu->src[0].src.ssa->bit_size != 64) return false; break; case nir_op_bcsel: - assert(alu->src[1].src.is_ssa); - assert(alu->src[2].src.is_ssa); assert(alu->src[1].src.ssa->bit_size == alu->src[2].src.ssa->bit_size); if (alu->src[1].src.ssa->bit_size != 64) @@ -1100,8 +1097,6 @@ should_lower_int64_alu_instr(const nir_alu_instr *alu, case nir_op_ilt: case nir_op_uge: case nir_op_ige: - assert(alu->src[0].src.is_ssa); - assert(alu->src[1].src.is_ssa); assert(alu->src[0].src.ssa->bit_size == alu->src[1].src.ssa->bit_size); if (alu->src[0].src.ssa->bit_size != 64) @@ -1110,12 +1105,10 @@ should_lower_int64_alu_instr(const nir_alu_instr *alu, case nir_op_ufind_msb: case nir_op_find_lsb: case nir_op_bit_count: - assert(alu->src[0].src.is_ssa); if (alu->src[0].src.ssa->bit_size != 64) return false; break; case nir_op_amul: - assert(alu->dest.dest.is_ssa); if (options->has_imul24) return false; if (alu->dest.dest.ssa.bit_size != 64) @@ -1127,7 +1120,6 @@ should_lower_int64_alu_instr(const nir_alu_instr *alu, case nir_op_u2f32: case nir_op_i2f16: case nir_op_u2f16: - assert(alu->src[0].src.is_ssa); if (alu->src[0].src.ssa->bit_size != 64) return false; break; @@ -1135,7 +1127,6 @@ should_lower_int64_alu_instr(const nir_alu_instr *alu, case nir_op_f2i64: FALLTHROUGH; default: - assert(alu->dest.dest.is_ssa); if (alu->dest.dest.ssa.bit_size != 64) return false; break; @@ -1239,7 +1230,6 @@ lower_scan_iadd64(nir_builder *b, const nir_intrinsic_instr *intrin) * no larger than 256 which seems reasonable.) We can then scan on each of * the chunks and add them back together at the end. */ - assert(intrin->src[0].is_ssa); nir_ssa_def *x = intrin->src[0].ssa; nir_ssa_def *x_low = nir_u2u32(b, nir_iand_imm(b, x, 0xffffff)); @@ -1281,19 +1271,16 @@ should_lower_int64_intrinsic(const nir_intrinsic_instr *intrin, case nir_intrinsic_quad_swap_horizontal: case nir_intrinsic_quad_swap_vertical: case nir_intrinsic_quad_swap_diagonal: - assert(intrin->dest.is_ssa); return intrin->dest.ssa.bit_size == 64 && (options->lower_int64_options & nir_lower_subgroup_shuffle64); case nir_intrinsic_vote_ieq: - assert(intrin->src[0].is_ssa); return intrin->src[0].ssa->bit_size == 64 && (options->lower_int64_options & nir_lower_vote_ieq64); case nir_intrinsic_reduce: case nir_intrinsic_inclusive_scan: case nir_intrinsic_exclusive_scan: - assert(intrin->dest.is_ssa); if (intrin->dest.ssa.bit_size != 64) return false; @@ -1331,7 +1318,6 @@ lower_int64_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin) return split_64bit_subgroup_op(b, intrin); case nir_intrinsic_vote_ieq: - assert(intrin->src[0].is_ssa); return lower_vote_ieq(b, intrin->src[0].ssa); case nir_intrinsic_reduce: diff --git a/src/compiler/nir/nir_lower_interpolation.c b/src/compiler/nir/nir_lower_interpolation.c index 4e4d96af627..3a854485f88 100644 --- a/src/compiler/nir/nir_lower_interpolation.c +++ b/src/compiler/nir/nir_lower_interpolation.c @@ -48,10 +48,6 @@ nir_lower_interpolation_instr(nir_builder *b, nir_instr *instr, void *cb_data) if (intr->intrinsic != nir_intrinsic_load_interpolated_input) return false; - assert(intr->dest.is_ssa); - assert(intr->src[0].is_ssa); - assert(intr->src[1].is_ssa); - nir_intrinsic_instr *bary_intrinsic = nir_instr_as_intrinsic(intr->src[0].ssa->parent_instr); diff --git a/src/compiler/nir/nir_lower_io.c b/src/compiler/nir/nir_lower_io.c index fc4be0ce534..4dbaceedd74 100644 --- a/src/compiler/nir/nir_lower_io.c +++ b/src/compiler/nir/nir_lower_io.c @@ -345,7 +345,6 @@ lower_load(nir_intrinsic_instr *intrin, struct lower_io_state *state, nir_ssa_def *array_index, nir_variable *var, nir_ssa_def *offset, unsigned component, const struct glsl_type *type) { - assert(intrin->dest.is_ssa); if (intrin->dest.ssa.bit_size == 64 && (state->options & nir_lower_io_lower_64bit_to_32)) { nir_builder *b = &state->builder; @@ -457,7 +456,6 @@ lower_store(nir_intrinsic_instr *intrin, struct lower_io_state *state, nir_ssa_def *array_index, nir_variable *var, nir_ssa_def *offset, unsigned component, const struct glsl_type *type) { - assert(intrin->src[1].is_ssa); if (intrin->src[1].ssa->bit_size == 64 && (state->options & nir_lower_io_lower_64bit_to_32)) { nir_builder *b = &state->builder; @@ -572,7 +570,6 @@ lower_interpolate_at(nir_intrinsic_instr *intrin, struct lower_io_state *state, var->data.precision == GLSL_PRECISION_MEDIUM || var->data.precision == GLSL_PRECISION_LOW; - assert(intrin->dest.is_ssa); nir_ssa_def *load = nir_load_interpolated_input(&state->builder, intrin->dest.ssa.num_components, @@ -1478,7 +1475,6 @@ build_explicit_io_load(nir_builder *b, nir_intrinsic_instr *intrin, nir_intrinsic_set_range(load, range); } - assert(intrin->dest.is_ssa); load->num_components = num_components; nir_ssa_dest_init(&load->instr, &load->dest, num_components, bit_size); @@ -1812,7 +1808,6 @@ nir_explicit_io_address_from_deref(nir_builder *b, nir_deref_instr *deref, nir_ssa_def *base_addr, nir_address_format addr_format) { - assert(deref->dest.is_ssa); switch (deref->deref_type) { case nir_deref_type_var: return build_addr_for_var(b, deref->var, addr_format); @@ -1914,7 +1909,6 @@ nir_lower_explicit_io_instr(nir_builder *b, } case nir_intrinsic_store_deref: { - assert(intrin->src[1].is_ssa); nir_ssa_def *value = intrin->src[1].ssa; nir_component_mask_t write_mask = nir_intrinsic_write_mask(intrin); if (vec_stride > scalar_size) { @@ -1949,7 +1943,6 @@ nir_lower_explicit_io_instr(nir_builder *b, } case nir_intrinsic_store_deref_block_intel: { - assert(intrin->src[1].is_ssa); nir_ssa_def *value = intrin->src[1].ssa; const nir_component_mask_t write_mask = 0; build_explicit_io_store(b, intrin, addr, addr_format, @@ -2093,7 +2086,6 @@ lower_explicit_io_deref(nir_builder *b, nir_deref_instr *deref, nir_ssa_def *base_addr = NULL; if (deref->deref_type != nir_deref_type_var) { - assert(deref->parent.is_ssa); base_addr = deref->parent.ssa; } @@ -2110,7 +2102,6 @@ static void lower_explicit_io_access(nir_builder *b, nir_intrinsic_instr *intrin, nir_address_format addr_format) { - assert(intrin->src[0].is_ssa); nir_lower_explicit_io_instr(b, intrin, intrin->src[0].ssa, addr_format); } @@ -2173,7 +2164,6 @@ lower_explicit_io_mode_check(nir_builder *b, nir_intrinsic_instr *intrin, return; } - assert(intrin->src[0].is_ssa); nir_ssa_def *addr = intrin->src[0].ssa; b->cursor = nir_instr_remove(&intrin->instr); diff --git a/src/compiler/nir/nir_lower_io_to_scalar.c b/src/compiler/nir/nir_lower_io_to_scalar.c index 083f8a140a0..bd4bfb4a9ff 100644 --- a/src/compiler/nir/nir_lower_io_to_scalar.c +++ b/src/compiler/nir/nir_lower_io_to_scalar.c @@ -45,8 +45,6 @@ lower_load_input_to_scalar(nir_builder *b, nir_intrinsic_instr *intr) { b->cursor = nir_before_instr(&intr->instr); - assert(intr->dest.is_ssa); - nir_ssa_def *loads[NIR_MAX_VEC_COMPONENTS]; for (unsigned i = 0; i < intr->num_components; i++) { @@ -79,8 +77,6 @@ lower_load_to_scalar(nir_builder *b, nir_intrinsic_instr *intr) { b->cursor = nir_before_instr(&intr->instr); - assert(intr->dest.is_ssa); - nir_ssa_def *loads[NIR_MAX_VEC_COMPONENTS]; nir_ssa_def *base_offset = nir_get_io_offset_src(intr)->ssa; @@ -326,8 +322,6 @@ lower_load_to_scalar_early(nir_builder *b, nir_intrinsic_instr *intr, { b->cursor = nir_before_instr(&intr->instr); - assert(intr->dest.is_ssa); - nir_ssa_def *loads[NIR_MAX_VEC_COMPONENTS]; nir_variable **chan_vars; diff --git a/src/compiler/nir/nir_lower_io_to_vector.c b/src/compiler/nir/nir_lower_io_to_vector.c index 85c87668bea..ee7558ed05e 100644 --- a/src/compiler/nir/nir_lower_io_to_vector.c +++ b/src/compiler/nir/nir_lower_io_to_vector.c @@ -562,7 +562,6 @@ nir_lower_io_to_vector_impl(nir_function_impl *impl, nir_variable_mode modes) nir_component_mask_t old_wrmask = nir_intrinsic_write_mask(intrin); - assert(intrin->src[1].is_ssa); nir_ssa_def *old_value = intrin->src[1].ssa; nir_ssa_scalar comps[4]; for (unsigned c = 0; c < intrin->num_components; c++) { diff --git a/src/compiler/nir/nir_lower_mem_access_bit_sizes.c b/src/compiler/nir/nir_lower_mem_access_bit_sizes.c index 3e6d7280efc..562e598ab25 100644 --- a/src/compiler/nir/nir_lower_mem_access_bit_sizes.c +++ b/src/compiler/nir/nir_lower_mem_access_bit_sizes.c @@ -40,7 +40,6 @@ dup_mem_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin, nir_src *intrin_offset_src = nir_get_io_offset_src(intrin); for (unsigned i = 0; i < info->num_srcs; i++) { - assert(intrin->src[i].is_ssa); if (i == 0 && data != NULL) { assert(!info->has_dest); assert(&intrin->src[i] != intrin_offset_src); @@ -59,7 +58,6 @@ dup_mem_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin, nir_intrinsic_set_align(dup, align_mul, align_offset); if (info->has_dest) { - assert(intrin->dest.is_ssa); nir_ssa_dest_init(&dup->instr, &dup->dest, num_components, bit_size); } else { nir_intrinsic_set_write_mask(dup, (1 << num_components) - 1); @@ -75,7 +73,6 @@ lower_mem_load(nir_builder *b, nir_intrinsic_instr *intrin, nir_lower_mem_access_bit_sizes_cb mem_access_size_align_cb, const void *cb_data) { - assert(intrin->dest.is_ssa); const unsigned bit_size = intrin->dest.ssa.bit_size; const unsigned num_components = intrin->dest.ssa.num_components; const unsigned bytes_read = num_components * (bit_size / 8); diff --git a/src/compiler/nir/nir_lower_memcpy.c b/src/compiler/nir/nir_lower_memcpy.c index fae3bfe0918..ba443479605 100644 --- a/src/compiler/nir/nir_lower_memcpy.c +++ b/src/compiler/nir/nir_lower_memcpy.c @@ -136,7 +136,6 @@ lower_memcpy_impl(nir_function_impl *impl) } } else { found_non_const_memcpy = true; - assert(cpy->src[2].is_ssa); nir_ssa_def *size = cpy->src[2].ssa; /* In this case, we don't have any idea what the size is so we diff --git a/src/compiler/nir/nir_lower_multiview.c b/src/compiler/nir/nir_lower_multiview.c index 8201c3f2839..8a7c3ccd465 100644 --- a/src/compiler/nir/nir_lower_multiview.c +++ b/src/compiler/nir/nir_lower_multiview.c @@ -275,7 +275,6 @@ nir_lower_multiview(nir_shader *shader, uint32_t view_mask) switch (intrin->intrinsic) { case nir_intrinsic_load_view_index: { - assert(intrin->dest.is_ssa); nir_ssa_def_rewrite_uses(&intrin->dest.ssa, view_index); break; } diff --git a/src/compiler/nir/nir_lower_non_uniform_access.c b/src/compiler/nir/nir_lower_non_uniform_access.c index 14fec922c95..06010532c92 100644 --- a/src/compiler/nir/nir_lower_non_uniform_access.c +++ b/src/compiler/nir/nir_lower_non_uniform_access.c @@ -48,7 +48,6 @@ nu_handle_init(struct nu_handle *h, nir_src *src) if (nir_src_is_const(deref->arr.index)) return false; - assert(deref->arr.index.is_ssa); h->handle = deref->arr.index.ssa; h->parent_deref = parent; diff --git a/src/compiler/nir/nir_lower_point_size.c b/src/compiler/nir/nir_lower_point_size.c index 3781b12e5e9..b725e7df845 100644 --- a/src/compiler/nir/nir_lower_point_size.c +++ b/src/compiler/nir/nir_lower_point_size.c @@ -51,7 +51,6 @@ lower_point_size_instr(nir_builder *b, nir_instr *instr, void *data) b->cursor = nir_before_instr(instr); - assert(intr->src[1].is_ssa); assert(intr->src[1].ssa->num_components == 1); nir_ssa_def *psiz = intr->src[1].ssa; diff --git a/src/compiler/nir/nir_lower_point_smooth.c b/src/compiler/nir/nir_lower_point_smooth.c index 6f1f993657a..c72e35edf6e 100644 --- a/src/compiler/nir/nir_lower_point_smooth.c +++ b/src/compiler/nir/nir_lower_point_smooth.c @@ -59,7 +59,6 @@ lower_point_smooth(nir_builder *b, nir_instr *instr, UNUSED void *_state) out_src_idx = 1; } - assert(intr->src[out_src_idx].is_ssa); assert(intr->num_components == 4); b->cursor = nir_before_instr(&intr->instr); diff --git a/src/compiler/nir/nir_lower_poly_line_smooth.c b/src/compiler/nir/nir_lower_poly_line_smooth.c index f9c9ff6d207..72064fe19d6 100644 --- a/src/compiler/nir/nir_lower_poly_line_smooth.c +++ b/src/compiler/nir/nir_lower_poly_line_smooth.c @@ -47,7 +47,6 @@ lower_polylinesmooth(nir_builder *b, nir_instr *instr, void *data) nir_intrinsic_src_type(intr) != nir_type_float32) return false; - assert(intr->src[0].is_ssa); assert(intr->num_components == 4); b->cursor = nir_before_instr(&intr->instr); diff --git a/src/compiler/nir/nir_lower_readonly_images_to_tex.c b/src/compiler/nir/nir_lower_readonly_images_to_tex.c index 9b4968e91ac..94ad203e483 100644 --- a/src/compiler/nir/nir_lower_readonly_images_to_tex.c +++ b/src/compiler/nir/nir_lower_readonly_images_to_tex.c @@ -137,13 +137,11 @@ lower_readonly_image_instr_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin switch (intrin->intrinsic) { case nir_intrinsic_image_deref_load: { - assert(intrin->src[1].is_ssa); nir_ssa_def *coord = nir_trim_vector(b, intrin->src[1].ssa, coord_components); tex->src[1] = nir_tex_src_for_ssa(nir_tex_src_coord, coord); tex->coord_components = coord_components; - assert(intrin->src[3].is_ssa); nir_ssa_def *lod = intrin->src[3].ssa; tex->src[2] = nir_tex_src_for_ssa(nir_tex_src_lod, lod); @@ -155,7 +153,6 @@ lower_readonly_image_instr_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin } case nir_intrinsic_image_deref_size: { - assert(intrin->src[1].is_ssa); nir_ssa_def *lod = intrin->src[1].ssa; tex->src[1] = nir_tex_src_for_ssa(nir_tex_src_lod, lod); diff --git a/src/compiler/nir/nir_lower_samplers.c b/src/compiler/nir/nir_lower_samplers.c index b5dd40c5d59..11e01ad49a2 100644 --- a/src/compiler/nir/nir_lower_samplers.c +++ b/src/compiler/nir/nir_lower_samplers.c @@ -39,7 +39,6 @@ lower_tex_src_to_offset(nir_builder *b, /* We compute first the offsets */ nir_deref_instr *deref = nir_instr_as_deref(src->src.ssa->parent_instr); while (deref->deref_type != nir_deref_type_var) { - assert(deref->parent.is_ssa); nir_deref_instr *parent = nir_instr_as_deref(deref->parent.ssa->parent_instr); diff --git a/src/compiler/nir/nir_lower_shader_calls.c b/src/compiler/nir/nir_lower_shader_calls.c index 12fdd7aa426..1cf81447e5f 100644 --- a/src/compiler/nir/nir_lower_shader_calls.c +++ b/src/compiler/nir/nir_lower_shader_calls.c @@ -914,7 +914,6 @@ rewrite_phis_to_pred(nir_block *block, nir_block *pred) nir_foreach_phi_src(phi_src, phi) { if (phi_src->pred == pred) { found = true; - assert(phi_src->src.is_ssa); nir_ssa_def_rewrite_uses(&phi->dest.ssa, phi_src->src.ssa); break; } diff --git a/src/compiler/nir/nir_lower_single_sampled.c b/src/compiler/nir/nir_lower_single_sampled.c index 5d793d8f2d0..65308fb9464 100644 --- a/src/compiler/nir/nir_lower_single_sampled.c +++ b/src/compiler/nir/nir_lower_single_sampled.c @@ -60,7 +60,6 @@ lower_single_sampled_instr(nir_builder *b, case nir_intrinsic_interp_deref_at_centroid: case nir_intrinsic_interp_deref_at_sample: b->cursor = nir_before_instr(instr); - assert(intrin->src[0].is_ssa); lowered = nir_load_deref(b, nir_src_as_deref(intrin->src[0])); break; diff --git a/src/compiler/nir/nir_lower_subgroups.c b/src/compiler/nir/nir_lower_subgroups.c index a393a0869e4..be7883ca02f 100644 --- a/src/compiler/nir/nir_lower_subgroups.c +++ b/src/compiler/nir/nir_lower_subgroups.c @@ -146,7 +146,6 @@ lower_subgroup_op_to_scalar(nir_builder *b, nir_intrinsic_instr *intrin, static nir_ssa_def * lower_vote_eq_to_scalar(nir_builder *b, nir_intrinsic_instr *intrin) { - assert(intrin->src[0].is_ssa); nir_ssa_def *value = intrin->src[0].ssa; nir_ssa_def *result = NULL; @@ -172,7 +171,6 @@ lower_vote_eq_to_scalar(nir_builder *b, nir_intrinsic_instr *intrin) static nir_ssa_def * lower_vote_eq(nir_builder *b, nir_intrinsic_instr *intrin) { - assert(intrin->src[0].is_ssa); nir_ssa_def *value = intrin->src[0].ssa; /* We have to implicitly lower to scalar */ @@ -244,22 +242,18 @@ lower_to_shuffle(nir_builder *b, nir_intrinsic_instr *intrin, bool is_shuffle = false; switch (intrin->intrinsic) { case nir_intrinsic_shuffle_xor: - assert(intrin->src[1].is_ssa); index = nir_ixor(b, index, intrin->src[1].ssa); is_shuffle = true; break; case nir_intrinsic_shuffle_up: - assert(intrin->src[1].is_ssa); index = nir_isub(b, index, intrin->src[1].ssa); is_shuffle = true; break; case nir_intrinsic_shuffle_down: - assert(intrin->src[1].is_ssa); index = nir_iadd(b, index, intrin->src[1].ssa); is_shuffle = true; break; case nir_intrinsic_quad_broadcast: - assert(intrin->src[1].is_ssa); index = nir_ior(b, nir_iand_imm(b, index, ~0x3), intrin->src[1].ssa); break; @@ -335,8 +329,6 @@ glsl_type_for_ssa(nir_ssa_def *def) static nir_ssa_def * lower_shuffle(nir_builder *b, nir_intrinsic_instr *intrin) { - assert(intrin->src[0].is_ssa); - assert(intrin->src[1].is_ssa); nir_ssa_def *val = intrin->src[0].ssa; nir_ssa_def *id = intrin->src[1].ssa; @@ -716,7 +708,6 @@ lower_subgroups_instr(nir_builder *b, nir_instr *instr, void *_options) case nir_intrinsic_ballot_bit_count_reduce: case nir_intrinsic_ballot_find_lsb: case nir_intrinsic_ballot_find_msb: { - assert(intrin->src[0].is_ssa); nir_ssa_def *int_val = ballot_type_to_uint(b, intrin->src[0].ssa, options); @@ -746,7 +737,6 @@ lower_subgroups_instr(nir_builder *b, nir_instr *instr, void *_options) switch (intrin->intrinsic) { case nir_intrinsic_ballot_bitfield_extract: { - assert(intrin->src[1].is_ssa); nir_ssa_def *idx = intrin->src[1].ssa; if (int_val->num_components > 1) { /* idx will be truncated by nir_ushr, so we just need to select @@ -773,7 +763,6 @@ lower_subgroups_instr(nir_builder *b, nir_instr *instr, void *_options) case nir_intrinsic_ballot_bit_count_exclusive: case nir_intrinsic_ballot_bit_count_inclusive: { - assert(intrin->src[0].is_ssa); nir_ssa_def *int_val = ballot_type_to_uint(b, intrin->src[0].ssa, options); if (options->lower_ballot_bit_count_to_mbcnt_amd) { diff --git a/src/compiler/nir/nir_lower_system_values.c b/src/compiler/nir/nir_lower_system_values.c index 6462ccdb826..0f21d2fdc00 100644 --- a/src/compiler/nir/nir_lower_system_values.c +++ b/src/compiler/nir/nir_lower_system_values.c @@ -42,7 +42,6 @@ struct lower_sysval_state { static nir_ssa_def * sanitize_32bit_sysval(nir_builder *b, nir_intrinsic_instr *intrin) { - assert(intrin->dest.is_ssa); const unsigned bit_size = intrin->dest.ssa.bit_size; if (bit_size == 32) return NULL; @@ -498,7 +497,6 @@ lower_compute_system_value_instr(nir_builder *b, if (!nir_intrinsic_infos[intrin->intrinsic].has_dest) return NULL; - assert(intrin->dest.is_ssa); const unsigned bit_size = intrin->dest.ssa.bit_size; switch (intrin->intrinsic) { diff --git a/src/compiler/nir/nir_lower_tex.c b/src/compiler/nir/nir_lower_tex.c index 8453adbe388..72c7a507d35 100644 --- a/src/compiler/nir/nir_lower_tex.c +++ b/src/compiler/nir/nir_lower_tex.c @@ -166,7 +166,6 @@ lower_offset(nir_builder *b, nir_tex_instr *tex) int coord_index = nir_tex_instr_src_index(tex, nir_tex_src_coord); assert(coord_index >= 0); - assert(tex->src[coord_index].src.is_ssa); nir_ssa_def *coord = tex->src[coord_index].src.ssa; b->cursor = nir_before_instr(&tex->instr); @@ -301,7 +300,6 @@ static nir_ssa_def * sample_plane(nir_builder *b, nir_tex_instr *tex, int plane, const nir_lower_tex_options *options) { - assert(tex->dest.is_ssa); assert(nir_tex_instr_dest_size(tex) == 4); assert(nir_alu_type_get_base_type(tex->dest_type) == nir_type_float); assert(tex->op == nir_texop_tex); @@ -660,7 +658,6 @@ lower_gradient_cube_map(nir_builder *b, nir_tex_instr *tex) { assert(tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE); assert(tex->op == nir_texop_txd); - assert(tex->dest.is_ssa); /* Use textureSize() to get the width and height of LOD 0 */ nir_ssa_def *size = nir_i2f32(b, nir_get_texture_size(b, tex)); @@ -813,7 +810,6 @@ lower_gradient(nir_builder *b, nir_tex_instr *tex) assert(tex->sampler_dim != GLSL_SAMPLER_DIM_CUBE); assert(tex->op == nir_texop_txd); - assert(tex->dest.is_ssa); /* Use textureSize() to get the width and height of LOD 0 */ unsigned component_mask; @@ -1015,8 +1011,6 @@ get_zero_or_one(nir_builder *b, nir_alu_type type, uint8_t swizzle_val) static void swizzle_tg4_broadcom(nir_builder *b, nir_tex_instr *tex) { - assert(tex->dest.is_ssa); - b->cursor = nir_after_instr(&tex->instr); assert(nir_tex_instr_dest_size(tex) == 4); @@ -1030,8 +1024,6 @@ swizzle_tg4_broadcom(nir_builder *b, nir_tex_instr *tex) static void swizzle_result(nir_builder *b, nir_tex_instr *tex, const uint8_t swizzle[4]) { - assert(tex->dest.is_ssa); - b->cursor = nir_after_instr(&tex->instr); nir_ssa_def *swizzled; @@ -1070,7 +1062,6 @@ swizzle_result(nir_builder *b, nir_tex_instr *tex, const uint8_t swizzle[4]) static void linearize_srgb_result(nir_builder *b, nir_tex_instr *tex) { - assert(tex->dest.is_ssa); assert(nir_tex_instr_dest_size(tex) == 4); assert(nir_alu_type_get_base_type(tex->dest_type) == nir_type_float); @@ -1299,7 +1290,6 @@ nir_lower_txs_cube_array(nir_builder *b, nir_tex_instr *tex) b->cursor = nir_after_instr(&tex->instr); - assert(tex->dest.is_ssa); assert(tex->dest.ssa.num_components == 3); nir_ssa_def *size = &tex->dest.ssa; size = nir_vec3(b, nir_channel(b, size, 1), @@ -1440,7 +1430,6 @@ lower_index_to_offset(nir_builder *b, nir_tex_instr *tex) if ((*index) == 0) continue; - assert(tex->src[i].src.is_ssa); nir_ssa_def *sum = nir_iadd_imm(b, tex->src[i].src.ssa, *index); nir_instr_rewrite_src(&tex->instr, &tex->src[i].src, nir_src_for_ssa(sum)); diff --git a/src/compiler/nir/nir_lower_two_sided_color.c b/src/compiler/nir/nir_lower_two_sided_color.c index 962d223134b..6ef55d60b94 100644 --- a/src/compiler/nir/nir_lower_two_sided_color.c +++ b/src/compiler/nir/nir_lower_two_sided_color.c @@ -164,7 +164,6 @@ nir_lower_two_sided_color_instr(nir_builder *b, nir_instr *instr, void *data) } nir_ssa_def *color = nir_bcsel(b, face, front, back); - assert(intr->dest.is_ssa); nir_ssa_def_rewrite_uses(&intr->dest.ssa, color); return true; diff --git a/src/compiler/nir/nir_lower_vars_to_ssa.c b/src/compiler/nir/nir_lower_vars_to_ssa.c index a9f6c703e30..99a41ecd1a9 100644 --- a/src/compiler/nir/nir_lower_vars_to_ssa.c +++ b/src/compiler/nir/nir_lower_vars_to_ssa.c @@ -603,8 +603,6 @@ rename_variables(struct lower_variables_state *state) for (unsigned i = intrin->num_components; i < NIR_MAX_VEC_COMPONENTS; i++) mov->src[0].swizzle[i] = 0; - assert(intrin->dest.is_ssa); - mov->dest.write_mask = (1 << intrin->num_components) - 1; nir_ssa_dest_init(&mov->instr, &mov->dest.dest, intrin->num_components, @@ -630,7 +628,6 @@ rename_variables(struct lower_variables_state *state) /* Should have been removed before rename_variables(). */ assert(node != UNDEF_NODE); - assert(intrin->src[1].is_ssa); nir_ssa_def *value = intrin->src[1].ssa; if (!node->lower_to_ssa) diff --git a/src/compiler/nir/nir_lower_vec3_to_vec4.c b/src/compiler/nir/nir_lower_vec3_to_vec4.c index 6d16ede3f2e..3d3d3d9363b 100644 --- a/src/compiler/nir/nir_lower_vec3_to_vec4.c +++ b/src/compiler/nir/nir_lower_vec3_to_vec4.c @@ -54,7 +54,6 @@ lower_vec3_to_vec4_instr(nir_builder *b, nir_instr *instr, void *data) if (!nir_deref_mode_is_in_set(deref, modes)) break; - assert(intrin->dest.is_ssa); intrin->num_components = 4; intrin->dest.ssa.num_components = 4; @@ -74,7 +73,6 @@ lower_vec3_to_vec4_instr(nir_builder *b, nir_instr *instr, void *data) if (!nir_deref_mode_is_in_set(deref, modes)) break; - assert(intrin->src[1].is_ssa); nir_ssa_def *data = intrin->src[1].ssa; b->cursor = nir_before_instr(&intrin->instr); diff --git a/src/compiler/nir/nir_lower_vec_to_regs.c b/src/compiler/nir/nir_lower_vec_to_regs.c index 8629e275668..dd878cd9a76 100644 --- a/src/compiler/nir/nir_lower_vec_to_regs.c +++ b/src/compiler/nir/nir_lower_vec_to_regs.c @@ -30,7 +30,6 @@ insert_store(nir_builder *b, nir_ssa_def *reg, nir_alu_instr *vec, unsigned start_idx) { assert(start_idx < nir_op_infos[vec->op].num_inputs); - assert(vec->src[start_idx].src.is_ssa); nir_ssa_def *src = vec->src[start_idx].src.ssa; unsigned num_components = nir_dest_num_components(vec->dest.dest); @@ -74,7 +73,6 @@ try_coalesce(nir_builder *b, nir_ssa_def *reg, nir_alu_instr *vec, unsigned start_idx, struct data *data) { assert(start_idx < nir_op_infos[vec->op].num_inputs); - assert(vec->src[start_idx].src.is_ssa); /* If we are going to do a reswizzle, then the vecN operation must be the * only use of the source value. @@ -201,7 +199,6 @@ lower(nir_builder *b, nir_instr *instr, void *data_) if (vec->op == nir_op_mov || !nir_op_is_vec(vec->op)) return false; - assert(vec->dest.dest.is_ssa); unsigned num_components = nir_dest_num_components(vec->dest.dest); /* Special case: if all sources are the same, just swizzle instead to avoid @@ -237,7 +234,6 @@ lower(nir_builder *b, nir_instr *instr, void *data_) unsigned swiz[NIR_MAX_VEC_COMPONENTS] = {0}; for (unsigned i = 0; i < num_components; ++i) { - assert(vec->src[i].src.is_ssa); swiz[i] = vec->src[i].swizzle[0]; } diff --git a/src/compiler/nir/nir_lower_wpos_center.c b/src/compiler/nir/nir_lower_wpos_center.c index 415981d785a..e275a46e59b 100644 --- a/src/compiler/nir/nir_lower_wpos_center.c +++ b/src/compiler/nir/nir_lower_wpos_center.c @@ -49,8 +49,6 @@ update_fragcoord(nir_builder *b, nir_intrinsic_instr *intr) { nir_ssa_def *wpos = &intr->dest.ssa; - assert(intr->dest.is_ssa); - b->cursor = nir_after_instr(&intr->instr); nir_ssa_def *spos = nir_load_sample_pos_or_center(b); diff --git a/src/compiler/nir/nir_lower_wpos_ytransform.c b/src/compiler/nir/nir_lower_wpos_ytransform.c index c56d6af5063..e2651ce622e 100644 --- a/src/compiler/nir/nir_lower_wpos_ytransform.c +++ b/src/compiler/nir/nir_lower_wpos_ytransform.c @@ -75,7 +75,6 @@ emit_wpos_adjustment(lower_wpos_ytransform_state *state, nir_builder *b = &state->b; nir_ssa_def *wpostrans, *wpos_temp, *wpos_temp_y, *wpos_input; - assert(intr->dest.is_ssa); wpos_input = &intr->dest.ssa; b->cursor = nir_after_instr(&intr->instr); diff --git a/src/compiler/nir/nir_opt_combine_stores.c b/src/compiler/nir/nir_opt_combine_stores.c index 654e1e28bd1..bd7c206fbeb 100644 --- a/src/compiler/nir/nir_opt_combine_stores.c +++ b/src/compiler/nir/nir_opt_combine_stores.c @@ -131,7 +131,6 @@ combine_stores(struct combine_stores_state *state, nir_intrinsic_instr *store = combo->stores[i]; if (combo->write_mask & (1 << i)) { assert(store); - assert(store->src[1].is_ssa); /* If store->num_components == 1 then we are in the deref-of-vec case * and store->src[1] is a scalar. Otherwise, we're a regular vector diff --git a/src/compiler/nir/nir_opt_conditional_discard.c b/src/compiler/nir/nir_opt_conditional_discard.c index e7ebb214ac3..e7140195e80 100644 --- a/src/compiler/nir/nir_opt_conditional_discard.c +++ b/src/compiler/nir/nir_opt_conditional_discard.c @@ -80,7 +80,6 @@ nir_opt_conditional_discard_block(nir_builder *b, nir_block *block) nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); nir_intrinsic_op op = intrin->intrinsic; - assert(if_stmt->condition.is_ssa); nir_ssa_def *cond = if_stmt->condition.ssa; b->cursor = nir_before_cf_node(prev_node); @@ -97,7 +96,6 @@ nir_opt_conditional_discard_block(nir_builder *b, nir_block *block) case nir_intrinsic_discard_if: case nir_intrinsic_demote_if: case nir_intrinsic_terminate_if: - assert(intrin->src[0].is_ssa); cond = nir_iand(b, cond, intrin->src[0].ssa); break; default: diff --git a/src/compiler/nir/nir_opt_dead_cf.c b/src/compiler/nir/nir_opt_dead_cf.c index 454f6f09464..e583305fff3 100644 --- a/src/compiler/nir/nir_opt_dead_cf.c +++ b/src/compiler/nir/nir_opt_dead_cf.c @@ -105,12 +105,10 @@ opt_constant_if(nir_if *if_stmt, bool condition) if (phi_src->pred != last_block) continue; - assert(phi_src->src.is_ssa); def = phi_src->src.ssa; } assert(def); - assert(phi->dest.is_ssa); nir_ssa_def_rewrite_uses(&phi->dest.ssa, def); nir_instr_remove(&phi->instr); } diff --git a/src/compiler/nir/nir_opt_idiv_const.c b/src/compiler/nir/nir_opt_idiv_const.c index 98950061c14..d44783b86b1 100644 --- a/src/compiler/nir/nir_opt_idiv_const.c +++ b/src/compiler/nir/nir_opt_idiv_const.c @@ -161,7 +161,6 @@ nir_opt_idiv_const_instr(nir_builder *b, nir_instr *instr, void *user_data) alu->op != nir_op_irem) return false; - assert(alu->dest.dest.is_ssa); assert(alu->src[0].src.is_ssa && alu->src[1].src.is_ssa); if (alu->dest.dest.ssa.bit_size < *min_bit_size) diff --git a/src/compiler/nir/nir_opt_if.c b/src/compiler/nir/nir_opt_if.c index 0aef197d4af..f62d047a3cf 100644 --- a/src/compiler/nir/nir_opt_if.c +++ b/src/compiler/nir/nir_opt_if.c @@ -1190,7 +1190,6 @@ clone_alu_and_replace_src_defs(nir_builder *b, const nir_alu_instr *alu, nalu->dest.write_mask = alu->dest.write_mask; for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) { - assert(alu->src[i].src.is_ssa); nalu->src[i].src = nir_src_for_ssa(src_defs[i]); nalu->src[i].negate = alu->src[i].negate; nalu->src[i].abs = alu->src[i].abs; @@ -1336,7 +1335,6 @@ opt_if_evaluate_condition_use(nir_builder *b, nir_if *nif) bool progress = false; /* Evaluate any uses of the if condition inside the if branches */ - assert(nif->condition.is_ssa); nir_foreach_use_including_if_safe(use_src, nif->condition.ssa) { if (!(use_src->is_if && use_src->parent_if == nif)) progress |= evaluate_condition_use(b, nif, use_src); diff --git a/src/compiler/nir/nir_opt_intrinsics.c b/src/compiler/nir/nir_opt_intrinsics.c index 18800cac46a..fe2a463b03b 100644 --- a/src/compiler/nir/nir_opt_intrinsics.c +++ b/src/compiler/nir/nir_opt_intrinsics.c @@ -45,9 +45,6 @@ src_is_single_use_shuffle(nir_src src, nir_ssa_def **data, nir_ssa_def **index) if (nir_ssa_def_used_by_if(&shuffle->dest.ssa)) return false; - assert(shuffle->src[0].is_ssa); - assert(shuffle->src[1].is_ssa); - *data = shuffle->src[0].ssa; *index = shuffle->src[1].ssa; diff --git a/src/compiler/nir/nir_opt_peephole_select.c b/src/compiler/nir/nir_opt_peephole_select.c index d173dd884ee..745f4ac8272 100644 --- a/src/compiler/nir/nir_opt_peephole_select.c +++ b/src/compiler/nir/nir_opt_peephole_select.c @@ -456,7 +456,6 @@ nir_opt_peephole_select_block(nir_block *block, nir_shader *shader, assert(exec_list_length(&phi->srcs) == 2); nir_foreach_phi_src(src, phi) { assert(src->pred == then_block || src->pred == else_block); - assert(src->src.is_ssa); unsigned idx = src->pred == then_block ? 1 : 2; nir_src_copy(&sel->src[idx].src, &src->src, &sel->instr); diff --git a/src/compiler/nir/nir_opt_phi_precision.c b/src/compiler/nir/nir_opt_phi_precision.c index 976c872daa1..85ef4832015 100644 --- a/src/compiler/nir/nir_opt_phi_precision.c +++ b/src/compiler/nir/nir_opt_phi_precision.c @@ -196,8 +196,6 @@ try_move_narrowing_dst(nir_builder *b, nir_phi_instr *phi) { nir_op op = INVALID_OP; - assert(phi->dest.is_ssa); - /* If the phi has already been narrowed, nothing more to do: */ if (phi->dest.ssa.bit_size != 32) return false; @@ -231,8 +229,6 @@ try_move_narrowing_dst(nir_builder *b, nir_phi_instr *phi) /* Push the conversion into the new phi sources: */ nir_foreach_phi_src (src, phi) { - assert(src->src.is_ssa); - /* insert new conversion instr in block of original phi src: */ b->cursor = nir_after_instr_and_phis(src->src.ssa->parent_instr); nir_ssa_def *old_src = src->src.ssa; @@ -306,8 +302,6 @@ find_widening_op(nir_phi_instr *phi, unsigned *bit_size) *bit_size = 0; nir_foreach_phi_src (src, phi) { - assert(src->src.is_ssa); - nir_instr *instr = src->src.ssa->parent_instr; if (instr->type == nir_instr_type_load_const) { has_load_const = true; @@ -344,8 +338,6 @@ find_widening_op(nir_phi_instr *phi, unsigned *bit_size) * sequence to make the rest of the transformation possible: */ nir_foreach_phi_src (src, phi) { - assert(src->src.is_ssa); - nir_instr *instr = src->src.ssa->parent_instr; if (instr->type != nir_instr_type_load_const) continue; @@ -363,8 +355,6 @@ find_widening_op(nir_phi_instr *phi, unsigned *bit_size) static bool try_move_widening_src(nir_builder *b, nir_phi_instr *phi) { - assert(phi->dest.is_ssa); - /* If the phi has already been narrowed, nothing more to do: */ if (phi->dest.ssa.bit_size != 32) return false; @@ -382,8 +372,6 @@ try_move_widening_src(nir_builder *b, nir_phi_instr *phi) /* Remove the widening conversions from the phi sources: */ nir_foreach_phi_src (src, phi) { - assert(src->src.is_ssa); - nir_instr *instr = src->src.ssa->parent_instr; nir_ssa_def *new_src; diff --git a/src/compiler/nir/nir_opt_remove_phis.c b/src/compiler/nir/nir_opt_remove_phis.c index 68e846c000c..f96879f25a2 100644 --- a/src/compiler/nir/nir_opt_remove_phis.c +++ b/src/compiler/nir/nir_opt_remove_phis.c @@ -74,8 +74,6 @@ remove_phis_block(nir_block *block, nir_builder *b) bool srcs_same = true; nir_foreach_phi_src(src, phi) { - assert(src->src.is_ssa); - /* For phi nodes at the beginning of loops, we may encounter some * sources from backedges that point back to the destination of the * same phi, i.e. something like: @@ -126,7 +124,6 @@ remove_phis_block(nir_block *block, nir_builder *b) def = nir_mov_alu(b, mov->src[0], def->num_components); } - assert(phi->dest.is_ssa); nir_ssa_def_rewrite_uses(&phi->dest.ssa, def); nir_instr_remove(&phi->instr); diff --git a/src/compiler/nir/nir_opt_undef.c b/src/compiler/nir/nir_opt_undef.c index effd9d0057a..6c096b76886 100644 --- a/src/compiler/nir/nir_opt_undef.c +++ b/src/compiler/nir/nir_opt_undef.c @@ -41,8 +41,6 @@ opt_undef_csel(nir_alu_instr *instr) if (!nir_op_is_selection(instr->op)) return false; - assert(instr->dest.dest.is_ssa); - for (int i = 1; i <= 2; i++) { if (!instr->src[i].src.is_ssa) continue; @@ -80,8 +78,6 @@ opt_undef_vecN(nir_builder *b, nir_alu_instr *alu) if (!nir_op_is_vec(alu->op)) return false; - assert(alu->dest.dest.is_ssa); - for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) { if (!alu->src[i].src.is_ssa || alu->src[i].src.ssa->parent_instr->type != nir_instr_type_ssa_undef) diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c index 6a9c608b3b2..e794cd27faf 100644 --- a/src/compiler/nir/nir_print.c +++ b/src/compiler/nir/nir_print.c @@ -862,7 +862,6 @@ print_deref_link(const nir_deref_instr *instr, bool whole_chain, print_state *st return; } - assert(instr->parent.is_ssa); nir_deref_instr *parent = nir_instr_as_deref(instr->parent.ssa->parent_instr); diff --git a/src/compiler/nir/nir_range_analysis.c b/src/compiler/nir/nir_range_analysis.c index 927eb6c0e56..908d88bf166 100644 --- a/src/compiler/nir/nir_range_analysis.c +++ b/src/compiler/nir/nir_range_analysis.c @@ -2106,7 +2106,6 @@ ssa_def_bits_used(const nir_ssa_def *def, int recur) case nir_intrinsic_quad_swap_vertical: case nir_intrinsic_quad_swap_diagonal: if (src_idx == 0) { - assert(use_intrin->dest.is_ssa); bits_used |= ssa_def_bits_used(&use_intrin->dest.ssa, recur); } else { if (use_intrin->intrinsic == nir_intrinsic_quad_broadcast) { diff --git a/src/compiler/nir/nir_schedule.c b/src/compiler/nir/nir_schedule.c index 83c0045cbff..4cc9307789f 100644 --- a/src/compiler/nir/nir_schedule.c +++ b/src/compiler/nir/nir_schedule.c @@ -234,7 +234,6 @@ static void nir_schedule_load_reg_deps(nir_intrinsic_instr *load, nir_deps_state *state) { - assert(load->src[0].is_ssa); nir_ssa_def *reg = load->src[0].ssa; (void)nir_reg_get_decl(reg); @@ -253,7 +252,6 @@ static void nir_schedule_store_reg_deps(nir_intrinsic_instr *store, nir_deps_state *state) { - assert(store->src[1].is_ssa); nir_ssa_def *reg = store->src[1].ssa; (void)nir_reg_get_decl(reg); @@ -554,7 +552,6 @@ nir_schedule_regs_freed_load_reg(nir_intrinsic_instr *load, nir_schedule_regs_freed_state *state) { assert(nir_is_load_reg(load)); - assert(load->src[0].is_ssa); if (load->intrinsic == nir_intrinsic_load_reg_indirect) nir_schedule_regs_freed_src_cb(&load->src[1], state); @@ -568,7 +565,6 @@ nir_schedule_regs_freed_load_reg(nir_intrinsic_instr *load, state->regs_freed += nir_schedule_reg_pressure(reg); } - assert(load->dest.is_ssa); nir_schedule_regs_freed_def_cb(&load->dest.ssa, state); } @@ -950,7 +946,6 @@ nir_schedule_mark_load_reg_scheduled(nir_intrinsic_instr *load, nir_schedule_scoreboard *scoreboard) { assert(nir_is_load_reg(load)); - assert(load->src[0].is_ssa); nir_ssa_def *reg = load->src[0].ssa; if (load->intrinsic == nir_intrinsic_load_reg_indirect) @@ -959,7 +954,6 @@ nir_schedule_mark_load_reg_scheduled(nir_intrinsic_instr *load, nir_schedule_mark_use(scoreboard, reg, &load->instr, nir_schedule_reg_pressure(reg)); - assert(load->dest.is_ssa); nir_schedule_mark_def_scheduled(&load->dest.ssa, scoreboard); } diff --git a/src/compiler/nir/nir_search.c b/src/compiler/nir/nir_search.c index 23ce9065f69..86f608f604b 100644 --- a/src/compiler/nir/nir_search.c +++ b/src/compiler/nir/nir_search.c @@ -229,15 +229,6 @@ match_value(const nir_algebraic_table *table, { uint8_t new_swizzle[NIR_MAX_VEC_COMPONENTS]; - /* Searching only works on SSA values because, if it's not SSA, we can't - * know if the value changed between one instance of that value in the - * expression and another. Also, the replace operation will place reads of - * that value right before the last instruction in the expression we're - * replacing so those reads will happen after the original reads and may - * not be valid if they're register reads. - */ - assert(instr->src[src].src.is_ssa); - /* If the source is an explicitly sized source, then we need to reset * both the number of components and the swizzle. */ @@ -370,8 +361,6 @@ match_expression(const nir_algebraic_table *table, const nir_search_expression * if (!nir_op_matches_search_op(instr->op, expr->opcode)) return false; - assert(instr->dest.dest.is_ssa); - if (expr->value.bit_size > 0 && instr->dest.dest.ssa.bit_size != expr->value.bit_size) return false; @@ -665,8 +654,6 @@ nir_replace_instr(nir_builder *build, nir_alu_instr *instr, for (unsigned i = 0; i < instr->dest.dest.ssa.num_components; ++i) swizzle[i] = i; - assert(instr->dest.dest.is_ssa); - struct match_state state; state.inexact_match = false; state.has_exact_alu = false; diff --git a/src/compiler/nir/nir_serialize.c b/src/compiler/nir/nir_serialize.c index 2bd34c50095..ed1081befd4 100644 --- a/src/compiler/nir/nir_serialize.c +++ b/src/compiler/nir/nir_serialize.c @@ -734,8 +734,6 @@ write_alu(write_ctx *ctx, const nir_alu_instr *alu) header.alu.op = alu->op; header.alu.packed_src_ssa_16bit = is_alu_src_ssa_16bit(ctx, alu); - assert(alu->dest.dest.is_ssa); - if (header.alu.packed_src_ssa_16bit) { /* For packed srcs of SSA ALUs, this field stores the swizzles. */ header.alu.writemask_or_two_swizzles = alu->src[0].swizzle[0]; @@ -747,7 +745,6 @@ write_alu(write_ctx *ctx, const nir_alu_instr *alu) if (header.alu.packed_src_ssa_16bit) { for (unsigned i = 0; i < num_srcs; i++) { - assert(alu->src[i].src.is_ssa); unsigned idx = write_lookup_object(ctx, alu->src[i].src.ssa); assert(idx < (1 << 16)); blob_write_uint16(ctx->blob, idx); @@ -1045,7 +1042,6 @@ read_deref(read_ctx *ctx, union packed_instr header) } else if (deref->deref_type == nir_deref_type_cast) { deref->modes = decode_deref_modes(header.deref.modes); } else { - assert(deref->parent.is_ssa); deref->modes = nir_instr_as_deref(deref->parent.ssa->parent_instr)->modes; } @@ -1483,7 +1479,6 @@ write_phi(write_ctx *ctx, const nir_phi_instr *phi) write_dest(ctx, &phi->dest, header, phi->instr.type); nir_foreach_phi_src(src, phi) { - assert(src->src.is_ssa); size_t blob_offset = blob_reserve_uint32(ctx->blob); ASSERTED size_t blob_offset2 = blob_reserve_uint32(ctx->blob); assert(blob_offset + sizeof(uint32_t) == blob_offset2); diff --git a/src/compiler/nir/nir_split_vars.c b/src/compiler/nir/nir_split_vars.c index 6b229876faa..dea2133008d 100644 --- a/src/compiler/nir/nir_split_vars.c +++ b/src/compiler/nir/nir_split_vars.c @@ -1174,8 +1174,6 @@ src_is_load_deref(nir_src src, nir_src deref_src) if (load == NULL || load->intrinsic != nir_intrinsic_load_deref) return false; - assert(load->src[0].is_ssa); - return load->src[0].ssa == deref_src.ssa; } @@ -1195,7 +1193,6 @@ get_non_self_referential_store_comps(nir_intrinsic_instr *store) { nir_component_mask_t comps = nir_intrinsic_write_mask(store); - assert(store->src[1].is_ssa); nir_instr *src_instr = store->src[1].ssa->parent_instr; if (src_instr->type != nir_instr_type_alu) return comps; diff --git a/src/compiler/nir/tests/vars_tests.cpp b/src/compiler/nir/tests/vars_tests.cpp index c60dd4b98bc..a79f97063bb 100644 --- a/src/compiler/nir/tests/vars_tests.cpp +++ b/src/compiler/nir/tests/vars_tests.cpp @@ -1975,7 +1975,6 @@ vec_src_comp_as_int(nir_src src, unsigned comp) if (nir_src_is_const(src)) return nir_src_comp_as_int(src, comp); - assert(src.is_ssa); nir_ssa_scalar s = { src.ssa, comp }; assert(nir_op_is_vec(nir_ssa_scalar_alu_op(s))); return nir_ssa_scalar_as_int(nir_ssa_scalar_chase_alu_src(s, comp)); diff --git a/src/freedreno/ir3/ir3_nir_lower_io_offsets.c b/src/freedreno/ir3/ir3_nir_lower_io_offsets.c index 9c017dbd0e1..b82268ad154 100644 --- a/src/freedreno/ir3/ir3_nir_lower_io_offsets.c +++ b/src/freedreno/ir3/ir3_nir_lower_io_offsets.c @@ -70,7 +70,6 @@ static nir_ssa_def * check_and_propagate_bit_shift32(nir_builder *b, nir_alu_instr *alu_instr, int32_t direction, int32_t shift) { - assert(alu_instr->src[1].src.is_ssa); nir_ssa_def *shift_ssa = alu_instr->src[1].src.ssa; /* Only propagate if the shift is a const value so we can check value range @@ -201,7 +200,6 @@ lower_offset_for_ssbo(nir_intrinsic_instr *intrinsic, nir_builder *b, /* 'offset_src_idx' holds the index of the source that represent the offset. */ new_intrinsic = nir_intrinsic_instr_create(b->shader, ir3_ssbo_opcode); - assert(intrinsic->src[offset_src_idx].is_ssa); nir_ssa_def *offset = intrinsic->src[offset_src_idx].ssa; /* Since we don't have value range checking, we first try to propagate @@ -221,7 +219,6 @@ lower_offset_for_ssbo(nir_intrinsic_instr *intrinsic, nir_builder *b, *target_src = nir_src_for_ssa(offset); if (has_dest) { - assert(intrinsic->dest.is_ssa); nir_ssa_def *dest = &intrinsic->dest.ssa; nir_ssa_dest_init(&new_intrinsic->instr, &new_intrinsic->dest, dest->num_components, dest->bit_size); diff --git a/src/freedreno/ir3/ir3_nir_lower_tex_prefetch.c b/src/freedreno/ir3/ir3_nir_lower_tex_prefetch.c index d1a9ed1ff44..a90e285ee65 100644 --- a/src/freedreno/ir3/ir3_nir_lower_tex_prefetch.c +++ b/src/freedreno/ir3/ir3_nir_lower_tex_prefetch.c @@ -193,7 +193,6 @@ lower_tex_prefetch_block(nir_block *block) int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord); /* First source should be the sampling coordinate. */ nir_tex_src *coord = &tex->src[idx]; - assert(coord->src.is_ssa); if (ir3_nir_coord_offset(coord->src.ssa) >= 0) { tex->op = nir_texop_tex_prefetch; diff --git a/src/freedreno/ir3/ir3_nir_move_varying_inputs.c b/src/freedreno/ir3/ir3_nir_move_varying_inputs.c index 0d2ce232a8b..908cb669a15 100644 --- a/src/freedreno/ir3/ir3_nir_move_varying_inputs.c +++ b/src/freedreno/ir3/ir3_nir_move_varying_inputs.c @@ -169,8 +169,6 @@ move_varying_inputs_block(state *state, nir_block *block) continue; } - assert(intr->dest.is_ssa); - move_instruction_to_start_block(state, instr); progress = true; diff --git a/src/freedreno/vulkan/tu_nir_lower_multiview.cc b/src/freedreno/vulkan/tu_nir_lower_multiview.cc index e0d9ff44239..500f80c65ff 100644 --- a/src/freedreno/vulkan/tu_nir_lower_multiview.cc +++ b/src/freedreno/vulkan/tu_nir_lower_multiview.cc @@ -49,7 +49,6 @@ lower_multiview_mask(nir_shader *nir, uint32_t *mask) if (var->data.location != VARYING_SLOT_POS) continue; - assert(intrin->src[1].is_ssa); nir_ssa_def *orig_src = intrin->src[1].ssa; b.cursor = nir_before_instr(instr); diff --git a/src/gallium/auxiliary/gallivm/lp_bld_nir.c b/src/gallium/auxiliary/gallivm/lp_bld_nir.c index 31a8d0f94ea..be4c14aa4e8 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_nir.c +++ b/src/gallium/auxiliary/gallivm/lp_bld_nir.c @@ -2341,7 +2341,6 @@ visit_intrinsic(struct lp_build_nir_context *bld_base, break; } if (result[0]) { - assert(instr->dest.is_ssa); assign_ssa_dest(bld_base, &instr->dest.ssa, result); } } @@ -2388,7 +2387,6 @@ visit_txs(struct lp_build_nir_context *bld_base, nir_tex_instr *instr) params.resource = resource; bld_base->tex_size(bld_base, ¶ms); - assert(instr->dest.is_ssa); assign_ssa_dest(bld_base, &instr->dest.ssa, &sizes_out[instr->op == nir_texop_query_levels ? 3 : 0]); } @@ -2699,7 +2697,6 @@ visit_tex(struct lp_build_nir_context *bld_base, nir_tex_instr *instr) } } - assert(instr->dest.is_ssa); assign_ssa_dest(bld_base, &instr->dest.ssa, texel); } diff --git a/src/gallium/auxiliary/nir/nir_to_tgsi.c b/src/gallium/auxiliary/nir/nir_to_tgsi.c index 53653b49b23..862655a96db 100644 --- a/src/gallium/auxiliary/nir/nir_to_tgsi.c +++ b/src/gallium/auxiliary/nir/nir_to_tgsi.c @@ -3594,8 +3594,6 @@ nir_to_tgsi_lower_tex_instr_arg(nir_builder *b, if (tex_src < 0) return; - assert(instr->src[tex_src].src.is_ssa); - nir_ssa_def *def = instr->src[tex_src].src.ssa; for (int i = 0; i < def->num_components; i++) { s->channels[s->i++] = nir_get_ssa_scalar(def, i); diff --git a/src/gallium/drivers/crocus/crocus_program.c b/src/gallium/drivers/crocus/crocus_program.c index f755f55f909..fa98c39a8de 100644 --- a/src/gallium/drivers/crocus/crocus_program.c +++ b/src/gallium/drivers/crocus/crocus_program.c @@ -669,8 +669,6 @@ crocus_setup_uniforms(ASSERTED const struct intel_device_info *devinfo, b.cursor = nir_before_instr(instr); - assert(load->src[0].is_ssa); - if (load->src[0].ssa == temp_ubo_name) { nir_ssa_def *imm = nir_imm_int(&b, sysval_cbuf_index); nir_instr_rewrite_src(instr, &load->src[0], diff --git a/src/gallium/drivers/d3d12/d3d12_nir_passes.c b/src/gallium/drivers/d3d12/d3d12_nir_passes.c index 0554b27a19f..2901b3b0cb7 100644 --- a/src/gallium/drivers/d3d12/d3d12_nir_passes.c +++ b/src/gallium/drivers/d3d12/d3d12_nir_passes.c @@ -137,7 +137,6 @@ lower_pos_read(nir_builder *b, struct nir_instr *instr, pos = nir_vector_insert_imm(b, pos, depth, 2); - assert(intr->dest.is_ssa); nir_ssa_def_rewrite_uses_after(&intr->dest.ssa, pos, pos->parent_instr); } diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c index 4ad6b5f0b06..437324bd910 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c +++ b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c @@ -611,7 +611,6 @@ emit_intrinsic(struct etna_compile *c, nir_intrinsic_instr * intr) } break; case nir_intrinsic_load_front_face: case nir_intrinsic_load_frag_coord: - assert(intr->dest.is_ssa); /* TODO - lower phis could cause this */ break; case nir_intrinsic_load_input: case nir_intrinsic_load_instance_id: diff --git a/src/gallium/drivers/freedreno/a2xx/ir2_nir.c b/src/gallium/drivers/freedreno/a2xx/ir2_nir.c index 368e97ceba4..5513d86229d 100644 --- a/src/gallium/drivers/freedreno/a2xx/ir2_nir.c +++ b/src/gallium/drivers/freedreno/a2xx/ir2_nir.c @@ -408,7 +408,6 @@ make_src_noconst(struct ir2_context *ctx, nir_src src) struct ir2_instr *instr; if (nir_src_as_const_value(src)) { - assert(src.is_ssa); instr = instr_create_alu(ctx, nir_op_mov, src.ssa->num_components); instr->src[0] = make_src(ctx, src); return ir2_src(instr->idx, 0, IR2_SRC_SSA); diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c index 02371230448..b54233c8d1c 100644 --- a/src/gallium/drivers/iris/iris_program.c +++ b/src/gallium/drivers/iris/iris_program.c @@ -706,8 +706,6 @@ iris_setup_uniforms(ASSERTED const struct intel_device_info *devinfo, b.cursor = nir_before_instr(instr); - assert(load->src[0].is_ssa); - if (load->src[0].ssa == temp_ubo_name) { nir_ssa_def *imm = nir_imm_int(&b, sysval_cbuf_index); nir_instr_rewrite_src(instr, &load->src[0], diff --git a/src/gallium/drivers/lima/ir/gp/nir.c b/src/gallium/drivers/lima/ir/gp/nir.c index c526c6175ba..1f1451e9093 100644 --- a/src/gallium/drivers/lima/ir/gp/nir.c +++ b/src/gallium/drivers/lima/ir/gp/nir.c @@ -251,8 +251,6 @@ static bool gpir_emit_intrinsic(gpir_block *block, nir_instr *ni) { gpir_node *child = gpir_node_find(block, &instr->src[0], 0); assert(child); - assert(instr->src[0].is_ssa); - assert(instr->src[1].is_ssa); register_node_reg(block, child, instr->src[1].ssa->index); return true; } diff --git a/src/gallium/drivers/lima/ir/lima_nir_split_loads.c b/src/gallium/drivers/lima/ir/lima_nir_split_loads.c index 942e22b9e59..6396e15249d 100644 --- a/src/gallium/drivers/lima/ir/lima_nir_split_loads.c +++ b/src/gallium/drivers/lima/ir/lima_nir_split_loads.c @@ -42,11 +42,8 @@ clone_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin) nir_intrinsic_instr *new_intrin = nir_instr_as_intrinsic(nir_instr_clone(b->shader, &intrin->instr)); - assert(new_intrin->dest.is_ssa); - unsigned num_srcs = nir_intrinsic_infos[new_intrin->intrinsic].num_srcs; for (unsigned i = 0; i < num_srcs; i++) { - assert(new_intrin->src[i].is_ssa); } nir_builder_instr_insert(b, &new_intrin->instr); diff --git a/src/gallium/drivers/lima/ir/pp/nir.c b/src/gallium/drivers/lima/ir/pp/nir.c index 995b46ae5e3..9e6f7a8f888 100644 --- a/src/gallium/drivers/lima/ir/pp/nir.c +++ b/src/gallium/drivers/lima/ir/pp/nir.c @@ -178,7 +178,6 @@ static bool ppir_emit_alu(ppir_block *block, nir_instr *ni) /* Add parent node as a the folded dest ssa node to keep * the dependency chain */ nir_alu_src *ns = &instr->src[0]; - assert(ns->src.is_ssa); ppir_node *parent = block->comp->var_nodes[ns->src.ssa->index]; assert(parent); block->comp->var_nodes[dst->ssa.index] = parent; @@ -321,7 +320,6 @@ static bool ppir_emit_intrinsic(ppir_block *block, nir_instr *ni) case nir_intrinsic_load_frag_coord: case nir_intrinsic_load_point_coord: case nir_intrinsic_load_front_face: { - assert(instr->dest.is_ssa); mask = u_bit_consecutive(0, instr->num_components); ppir_op op; diff --git a/src/gallium/drivers/r600/sfn/sfn_nir.cpp b/src/gallium/drivers/r600/sfn/sfn_nir.cpp index 735f66ffb0c..fab8a7dff64 100644 --- a/src/gallium/drivers/r600/sfn/sfn_nir.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_nir.cpp @@ -407,7 +407,6 @@ r600_lower_deref_instr(nir_builder *b, nir_instr *instr_, UNUSED void *cb_data) for (nir_deref_instr *d = deref; d->deref_type != nir_deref_type_var; d = nir_deref_instr_parent(d)) { assert(d->deref_type == nir_deref_type_array); - assert(d->arr.index.is_ssa); unsigned array_stride = 1; if (glsl_type_is_array(d->type)) diff --git a/src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp b/src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp index 6e2b14e5b04..f1e7856cb2e 100644 --- a/src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp @@ -121,7 +121,6 @@ LowerLoad64Uniform::lower(nir_instr *instr) auto intr = nir_instr_as_intrinsic(instr); int old_components = nir_dest_num_components(intr->dest); assert(old_components <= 2); - assert(intr->dest.is_ssa); intr->dest.ssa.num_components *= 2; intr->dest.ssa.bit_size = 32; intr->num_components *= 2; diff --git a/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp b/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp index 8d1697ea179..54e8525ec12 100644 --- a/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp @@ -212,8 +212,6 @@ update_alu_mask(nir_src *src, void *data) static uint32_t get_dest_usee_mask(nir_intrinsic_instr *op) { - assert(op->dest.is_ssa); - MaskQuery mq = {0}; mq.full_mask = (1 << nir_dest_num_components(op->dest)) - 1; diff --git a/src/gallium/drivers/r600/sfn/sfn_nir_vectorize_vs_inputs.c b/src/gallium/drivers/r600/sfn/sfn_nir_vectorize_vs_inputs.c index e2037b78534..d12e961c16e 100644 --- a/src/gallium/drivers/r600/sfn/sfn_nir_vectorize_vs_inputs.c +++ b/src/gallium/drivers/r600/sfn/sfn_nir_vectorize_vs_inputs.c @@ -146,8 +146,6 @@ r600_create_new_load(nir_builder *b, b->cursor = nir_before_instr(&intr->instr); - assert(intr->dest.is_ssa); - nir_intrinsic_instr *new_intr = nir_intrinsic_instr_create(b->shader, intr->intrinsic); nir_ssa_dest_init(&new_intr->instr, &new_intr->dest, num_comps, intr->dest.ssa.bit_size); diff --git a/src/gallium/drivers/r600/sfn/sfn_valuefactory.cpp b/src/gallium/drivers/r600/sfn/sfn_valuefactory.cpp index d9af52a914f..d995ffe3960 100644 --- a/src/gallium/drivers/r600/sfn/sfn_valuefactory.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_valuefactory.cpp @@ -170,7 +170,6 @@ ValueFactory::allocate_pinned_vec4(int sel, bool is_ssa) void ValueFactory::inject_value(const nir_dest& dest, int chan, PVirtualValue value) { - assert(dest.is_ssa); RegisterKey key(dest.ssa.index, chan, vp_ssa); sfn_log << SfnLog::reg << "Inject value with key " << key << "\n"; assert(m_values.find(key) == m_values.end()); @@ -211,7 +210,6 @@ public: PRegister ValueFactory::dest(const nir_dest& dst, int chan, Pin pin_channel, uint8_t chan_mask) { - assert(dst.is_ssa); return dest(dst.ssa, chan, pin_channel, chan_mask); } @@ -283,7 +281,6 @@ ValueFactory::dest_vec4(const nir_dest& dst, Pin pin) { if (pin != pin_group && pin != pin_chgr) pin = pin_chan; - assert(dst.is_ssa); PRegister x = dest(dst, 0, pin); PRegister y = dest(dst, 1, pin); PRegister z = dest(dst, 2, pin); @@ -331,7 +328,6 @@ ValueFactory::src(const nir_src& src, int chan) { sfn_log << SfnLog::reg << "search (ref) " << (void *)&src << "\n"; - assert(src.is_ssa); sfn_log << SfnLog::reg << "search ssa " << src.ssa->index << " c:" << chan << " got "; auto val = ssa_src(*src.ssa, chan); diff --git a/src/gallium/drivers/vc4/vc4_nir_lower_txf_ms.c b/src/gallium/drivers/vc4/vc4_nir_lower_txf_ms.c index d691ec43e22..bf0e6b55b00 100644 --- a/src/gallium/drivers/vc4/vc4_nir_lower_txf_ms.c +++ b/src/gallium/drivers/vc4/vc4_nir_lower_txf_ms.c @@ -51,8 +51,6 @@ vc4_nir_lower_txf_ms_instr(nir_builder *b, nir_instr *instr, void *data) nir_ssa_def *coord = NULL, *sample_index = NULL; for (int i = 0; i < txf_ms->num_srcs; i++) { - assert(txf_ms->src[i].src.is_ssa); - switch (txf_ms->src[i].src_type) { case nir_tex_src_coord: coord = txf_ms->src[i].src.ssa; diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c index 1881512f851..0e34464d210 100644 --- a/src/gallium/drivers/vc4/vc4_program.c +++ b/src/gallium/drivers/vc4/vc4_program.c @@ -257,7 +257,6 @@ ntq_get_src(struct vc4_compile *c, nir_src src, int i) { struct hash_entry *entry; - assert(src.is_ssa); nir_intrinsic_instr *load = nir_load_reg_for_def(src.ssa); if (load == NULL) { entry = _mesa_hash_table_search(c->def_ht, src.ssa); @@ -830,7 +829,6 @@ ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr) /* If packing from a vec4 op (as expected), identify it so that we can * peek back at what generated its sources. */ - assert(instr->src[0].src.is_ssa); if (instr->src[0].src.ssa->parent_instr->type == nir_instr_type_alu && nir_instr_as_alu(instr->src[0].src.ssa->parent_instr)->op == nir_op_vec4) { @@ -997,7 +995,6 @@ ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest, static struct qreg ntq_emit_bcsel(struct vc4_compile *c, nir_alu_instr *instr, struct qreg *src) { - assert(instr->src[0].src.is_ssa); if (nir_load_reg_for_def(instr->src[0].src.ssa)) goto out; if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu) diff --git a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c index b02d19ef18e..a7be604e79e 100644 --- a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c +++ b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c @@ -3451,11 +3451,9 @@ emit_is_sparse_texels_resident(struct ntv_context *ctx, nir_intrinsic_instr *int SpvId type = get_dest_type(ctx, &intr->dest, nir_type_uint); /* this will always be stored with the ssa index of the parent instr */ - assert(intr->src[0].is_ssa); nir_ssa_def *ssa = intr->src[0].ssa; assert(ssa->parent_instr->type == nir_instr_type_alu); nir_alu_instr *alu = nir_instr_as_alu(ssa->parent_instr); - assert(alu->src[0].src.is_ssa); unsigned index = alu->src[0].src.ssa->index; assert(index < ctx->num_defs); assert(ctx->resident_defs[index] != 0); diff --git a/src/gallium/drivers/zink/zink_compiler.c b/src/gallium/drivers/zink/zink_compiler.c index dbf412d3719..fc0a5663d89 100644 --- a/src/gallium/drivers/zink/zink_compiler.c +++ b/src/gallium/drivers/zink/zink_compiler.c @@ -433,7 +433,6 @@ replicate_derefs(nir_builder *b, nir_deref_instr *old, nir_deref_instr *new) case nir_deref_type_var: return new; case nir_deref_type_array: - assert(old->arr.index.is_ssa); return nir_build_deref_array(b, replicate_derefs(b, parent, new), old->arr.index.ssa); case nir_deref_type_struct: return nir_build_deref_struct(b, replicate_derefs(b, parent, new), old->strct.index); @@ -458,7 +457,6 @@ lower_pv_mode_gs_store(nir_builder *b, gl_varying_slot location = var->data.location; unsigned location_frac = var->data.location_frac; assert(state->varyings[location][location_frac]); - assert(intrin->src[1].is_ssa); nir_ssa_def *pos_counter = nir_load_var(b, state->pos_counter); nir_ssa_def *index = lower_pv_mode_gs_ring_index(b, state, pos_counter); nir_deref_instr *varying_deref = nir_build_deref_var(b, state->varyings[location][location_frac]); @@ -889,7 +887,6 @@ lower_line_smooth_gs_store(nir_builder *b, unsigned location_frac = var->data.location_frac; if (location != VARYING_SLOT_POS) { assert(state->varyings[location]); - assert(intrin->src[1].is_ssa); nir_store_var(b, state->varyings[location][location_frac], intrin->src[1].ssa, nir_intrinsic_write_mask(intrin)); @@ -1713,7 +1710,6 @@ lower_txf_lod_robustness_instr(nir_builder *b, nir_instr *in, void *data) if (nir_src_is_const(lod_src) && nir_src_as_const_value(lod_src)->u32 == 0) return false; - assert(lod_src.is_ssa); nir_ssa_def *lod = lod_src.ssa; int offset_idx = nir_tex_instr_src_index(txf, nir_tex_src_texture_offset); diff --git a/src/gallium/frontends/rusticl/rusticl_nir.c b/src/gallium/frontends/rusticl/rusticl_nir.c index 8669fa50793..40c9c4b2f93 100644 --- a/src/gallium/frontends/rusticl/rusticl_nir.c +++ b/src/gallium/frontends/rusticl/rusticl_nir.c @@ -23,8 +23,6 @@ rusticl_lower_intrinsics_instr( switch (intrins->intrinsic) { case nir_intrinsic_image_deref_format: case nir_intrinsic_image_deref_order: { - assert(intrins->src[0].is_ssa); - int32_t offset; nir_deref_instr *deref; nir_ssa_def *val; diff --git a/src/imagination/rogue/nir/rogue_nir_lower_io.c b/src/imagination/rogue/nir/rogue_nir_lower_io.c index 45af630c727..b633444d8a4 100644 --- a/src/imagination/rogue/nir/rogue_nir_lower_io.c +++ b/src/imagination/rogue/nir/rogue_nir_lower_io.c @@ -59,7 +59,6 @@ static void lower_load_global_constant_to_scalar(nir_builder *b, /* Scalarize the load_global_constant. */ b->cursor = nir_before_instr(&intr->instr); - assert(intr->dest.is_ssa); assert(intr->num_components > 1); nir_ssa_def *loads[NIR_MAX_VEC_COMPONENTS]; diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 8a0cee85233..5e141dc88c1 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -496,7 +496,6 @@ bool fs_visitor::optimize_extract_to_float(nir_alu_instr *instr, const fs_reg &result) { - assert(instr->src[0].src.is_ssa); if (!instr->src[0].src.ssa->parent_instr) return false; @@ -982,13 +981,11 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, fs_reg temp = result; bool need_extra_copy = false; - assert(instr->dest.dest.is_ssa); nir_intrinsic_instr *store_reg = nir_store_reg_for_def(&instr->dest.dest.ssa); if (store_reg != NULL) { nir_ssa_def *dest_reg = store_reg->src[1].ssa; for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) { - assert(instr->src[i].src.is_ssa); nir_intrinsic_instr *load_reg = nir_load_reg_for_def(instr->src[i].src.ssa); if (load_reg == NULL) @@ -1977,16 +1974,12 @@ fs_visitor::nir_emit_load_const(const fs_builder &bld, bool fs_visitor::get_nir_src_bindless(const nir_src &src) { - assert(src.is_ssa); - return nir_ssa_bind_infos[src.ssa->index].bindless; } unsigned fs_visitor::get_nir_src_block(const nir_src &src) { - assert(src.is_ssa); - return nir_ssa_bind_infos[src.ssa->index].valid ? nir_ssa_bind_infos[src.ssa->index].block : UINT32_MAX; @@ -1995,7 +1988,6 @@ fs_visitor::get_nir_src_block(const nir_src &src) static bool is_resource_src(nir_src src) { - assert(src.is_ssa); return src.ssa->parent_instr->type == nir_instr_type_intrinsic && nir_instr_as_intrinsic(src.ssa->parent_instr)->intrinsic == nir_intrinsic_resource_intel; } @@ -2011,7 +2003,6 @@ fs_visitor::get_resource_nir_src(const nir_src &src) fs_reg fs_visitor::get_nir_src(const nir_src &src) { - assert(src.is_ssa); nir_intrinsic_instr *load_reg = nir_load_reg_for_def(src.ssa); fs_reg reg; @@ -2067,7 +2058,6 @@ fs_visitor::get_nir_src_imm(const nir_src &src) fs_reg fs_visitor::get_nir_dest(const nir_dest &dest) { - assert(dest.is_ssa); nir_intrinsic_instr *store_reg = nir_store_reg_for_def(&dest.ssa); if (!store_reg) { const brw_reg_type reg_type = @@ -2092,7 +2082,6 @@ fs_visitor::get_nir_dest(const nir_dest &dest) nir_component_mask_t fs_visitor::get_nir_write_mask(const nir_alu_dest &dest) { - assert(dest.dest.is_ssa); assert(dest.write_mask == nir_component_mask(dest.dest.ssa.num_components)); nir_intrinsic_instr *store_reg = nir_store_reg_for_def(&dest.dest.ssa); @@ -6711,7 +6700,6 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr) const unsigned dest_size = nir_tex_instr_dest_size(instr); if (devinfo->ver >= 9 && instr->op != nir_texop_tg4 && instr->op != nir_texop_query_levels) { - assert(instr->dest.is_ssa); unsigned write_mask = nir_ssa_def_components_read(&instr->dest.ssa); assert(write_mask != 0); /* dead code should have been eliminated */ if (instr->is_sparse) { diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index e939a0edd94..206dceb020a 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -41,10 +41,8 @@ remap_tess_levels(nir_builder *b, nir_intrinsic_instr *intr, nir_ssa_def *src = NULL, *dest = NULL; if (write) { - assert(intr->src[0].is_ssa); assert(intr->num_components == intr->src[0].ssa->num_components); } else { - assert(intr->dest.is_ssa); assert(intr->num_components == intr->dest.ssa.num_components); } @@ -764,13 +762,11 @@ lower_bit_size_callback(const nir_instr *instr, UNUSED void *data) * 32-bit and so the bit size of the instruction is given by the * source. */ - assert(alu->src[0].src.is_ssa); return alu->src[0].src.ssa->bit_size >= 32 ? 0 : 32; default: break; } - assert(alu->dest.dest.is_ssa); if (alu->dest.dest.ssa.bit_size >= 32) return 0; @@ -2056,8 +2052,6 @@ brw_nir_load_global_const(nir_builder *b, nir_intrinsic_instr *load_uniform, nir_ssa_def *base_addr, unsigned off) { assert(load_uniform->intrinsic == nir_intrinsic_load_uniform); - assert(load_uniform->dest.is_ssa); - assert(load_uniform->src[0].is_ssa); unsigned bit_size = load_uniform->dest.ssa.bit_size; assert(bit_size >= 8 && bit_size % 8 == 0); diff --git a/src/intel/compiler/brw_nir_lower_conversions.c b/src/intel/compiler/brw_nir_lower_conversions.c index a15adb52e8a..52bbdf43676 100644 --- a/src/intel/compiler/brw_nir_lower_conversions.c +++ b/src/intel/compiler/brw_nir_lower_conversions.c @@ -114,7 +114,6 @@ lower_instr(nir_builder *b, nir_instr *instr, UNUSED void *cb_data) return false; nir_alu_instr *alu = nir_instr_as_alu(instr); - assert(alu->dest.dest.is_ssa); if (!nir_op_infos[alu->op].is_conversion) return false; diff --git a/src/intel/compiler/brw_nir_lower_shading_rate_output.c b/src/intel/compiler/brw_nir_lower_shading_rate_output.c index 7cecbe15b79..0a15a0e27b0 100644 --- a/src/intel/compiler/brw_nir_lower_shading_rate_output.c +++ b/src/intel/compiler/brw_nir_lower_shading_rate_output.c @@ -72,7 +72,6 @@ lower_shading_rate_output_instr(nir_builder *b, nir_instr *instr, b->cursor = is_store ? nir_before_instr(instr) : nir_after_instr(instr); if (is_store) { - assert(intrin->src[0].is_ssa); nir_ssa_def *bit_field = intrin->src[0].ssa; nir_ssa_def *fp16_x = nir_i2f16(b, diff --git a/src/intel/compiler/brw_nir_opt_peephole_ffma.c b/src/intel/compiler/brw_nir_opt_peephole_ffma.c index 2ef6800f2f1..0b66689ccfc 100644 --- a/src/intel/compiler/brw_nir_opt_peephole_ffma.c +++ b/src/intel/compiler/brw_nir_opt_peephole_ffma.c @@ -48,7 +48,6 @@ are_all_uses_fadd(nir_ssa_def *def) case nir_op_mov: case nir_op_fneg: case nir_op_fabs: - assert(use_alu->dest.dest.is_ssa); if (!are_all_uses_fadd(&use_alu->dest.dest.ssa)) return false; break; @@ -167,7 +166,6 @@ brw_nir_opt_peephole_ffma_instr(nir_builder *b, if (add->op != nir_op_fadd) return false; - assert(add->dest.dest.is_ssa); if (add->exact) return false; @@ -237,8 +235,6 @@ brw_nir_opt_peephole_ffma_instr(nir_builder *b, } nir_alu_src_copy(&ffma->src[2], &add->src[1 - add_mul_src], ffma); - assert(add->dest.dest.is_ssa); - nir_ssa_dest_init(&ffma->instr, &ffma->dest.dest, add->dest.dest.ssa.num_components, bit_size); nir_ssa_def_rewrite_uses(&add->dest.dest.ssa, &ffma->dest.dest.ssa); diff --git a/src/intel/compiler/brw_nir_rt.c b/src/intel/compiler/brw_nir_rt.c index eb821cfc5c0..245202db6a2 100644 --- a/src/intel/compiler/brw_nir_rt.c +++ b/src/intel/compiler/brw_nir_rt.c @@ -28,7 +28,6 @@ static bool resize_deref(nir_builder *b, nir_deref_instr *deref, unsigned num_components, unsigned bit_size) { - assert(deref->dest.is_ssa); if (deref->dest.ssa.num_components == num_components && deref->dest.ssa.bit_size == bit_size) return false; @@ -38,7 +37,6 @@ resize_deref(nir_builder *b, nir_deref_instr *deref, (deref->deref_type == nir_deref_type_array || deref->deref_type == nir_deref_type_ptr_as_array)) { b->cursor = nir_before_instr(&deref->instr); - assert(deref->arr.index.is_ssa); nir_ssa_def *idx; if (nir_src_is_const(deref->arr.index)) { idx = nir_imm_intN_t(b, nir_src_as_int(deref->arr.index), bit_size); @@ -522,7 +520,6 @@ brw_nir_create_raygen_trampoline(const struct brw_compiler *compiler, b.cursor = nir_before_instr(&intrin->instr); nir_ssa_def *global_arg_addr = load_trampoline_param(&b, rt_disp_globals_addr, 1, 64); - assert(intrin->dest.is_ssa); nir_ssa_def_rewrite_uses(&intrin->dest.ssa, global_arg_addr); nir_instr_remove(instr); diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp index 4fec7cb9865..fb2fa8e1e76 100644 --- a/src/intel/compiler/brw_vec4_nir.cpp +++ b/src/intel/compiler/brw_vec4_nir.cpp @@ -185,7 +185,6 @@ dst_reg_for_nir_reg(vec4_visitor *v, nir_ssa_def *handle, dst_reg vec4_visitor::get_nir_dest(const nir_dest &dest) { - assert(dest.is_ssa); nir_intrinsic_instr *store_reg = nir_store_reg_for_def(&dest.ssa); if (!store_reg) { dst_reg dst = @@ -223,7 +222,6 @@ src_reg vec4_visitor::get_nir_src(const nir_src &src, enum brw_reg_type type, unsigned num_components) { - assert(src.is_ssa); nir_intrinsic_instr *load_reg = nir_load_reg_for_def(src.ssa); dst_reg reg; diff --git a/src/intel/vulkan/anv_mesh_perprim_wa.c b/src/intel/vulkan/anv_mesh_perprim_wa.c index c40b23c5cb1..c1a4a30d342 100644 --- a/src/intel/vulkan/anv_mesh_perprim_wa.c +++ b/src/intel/vulkan/anv_mesh_perprim_wa.c @@ -451,9 +451,6 @@ anv_frag_update_derefs_instr(struct nir_builder *b, nir_instr *instr, void *data if (new_derefs[location] == NULL) return false; - assert(deref->dest.is_ssa); - assert(new_derefs[location]->dest.is_ssa); - nir_instr_remove(&deref->instr); nir_ssa_def_rewrite_uses(&deref->dest.ssa, &new_derefs[location]->dest.ssa); diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c index aa7a92fccea..e65ca3fc6a5 100644 --- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c +++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c @@ -1043,7 +1043,6 @@ build_load_var_deref_surface_handle(nir_builder *b, nir_deref_instr *deref, if (deref->deref_type != nir_deref_type_var) { assert(deref->deref_type == nir_deref_type_array); assert(nir_deref_instr_parent(deref)->deref_type == nir_deref_type_var); - assert(deref->arr.index.is_ssa); array_index = deref->arr.index.ssa; } else { array_index = nir_imm_int(b, 0); @@ -1068,7 +1067,6 @@ build_res_index_for_chain(nir_builder *b, nir_intrinsic_instr *intrin, { if (intrin->intrinsic == nir_intrinsic_vulkan_resource_index) { b->cursor = nir_before_instr(&intrin->instr); - assert(intrin->src[0].is_ssa); *set = nir_intrinsic_desc_set(intrin); *binding = nir_intrinsic_binding(intrin); return build_res_index(b, *set, *binding, intrin->src[0].ssa, state); @@ -1081,7 +1079,6 @@ build_res_index_for_chain(nir_builder *b, nir_intrinsic_instr *intrin, b->cursor = nir_before_instr(&intrin->instr); - assert(intrin->src[1].is_ssa); return build_res_reindex(b, index, intrin->src[1].ssa); } } @@ -1261,7 +1258,6 @@ lower_load_accel_struct_desc(nir_builder *b, /* Acceleration structure descriptors are always uint64_t */ nir_ssa_def *desc = build_load_descriptor_mem(b, desc_addr, 0, 1, 64, state); - assert(load_desc->dest.is_ssa); assert(load_desc->dest.ssa.bit_size == 64); assert(load_desc->dest.ssa.num_components == 1); nir_ssa_def_rewrite_uses(&load_desc->dest.ssa, desc); @@ -1340,14 +1336,12 @@ lower_res_index_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin, { b->cursor = nir_before_instr(&intrin->instr); - assert(intrin->src[0].is_ssa); nir_ssa_def *index = build_res_index(b, nir_intrinsic_desc_set(intrin), nir_intrinsic_binding(intrin), intrin->src[0].ssa, state); - assert(intrin->dest.is_ssa); assert(intrin->dest.ssa.bit_size == index->bit_size); assert(intrin->dest.ssa.num_components == index->num_components); nir_ssa_def_rewrite_uses(&intrin->dest.ssa, index); @@ -1367,7 +1361,6 @@ lower_res_reindex_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin, build_res_reindex(b, intrin->src[0].ssa, intrin->src[1].ssa); - assert(intrin->dest.is_ssa); assert(intrin->dest.ssa.bit_size == index->bit_size); assert(intrin->dest.ssa.num_components == index->num_components); nir_ssa_def_rewrite_uses(&intrin->dest.ssa, index); @@ -1385,13 +1378,11 @@ lower_load_vulkan_descriptor(nir_builder *b, nir_intrinsic_instr *intrin, const VkDescriptorType desc_type = nir_intrinsic_desc_type(intrin); nir_address_format addr_format = addr_format_for_desc_type(desc_type, state); - assert(intrin->src[0].is_ssa); nir_ssa_def *desc = build_buffer_addr_for_res_index(b, desc_type, intrin->src[0].ssa, addr_format, state); - assert(intrin->dest.is_ssa); assert(intrin->dest.ssa.bit_size == desc->bit_size); assert(intrin->dest.ssa.num_components == desc->num_components); nir_ssa_def_rewrite_uses(&intrin->dest.ssa, desc); @@ -1412,7 +1403,6 @@ lower_get_ssbo_size(nir_builder *b, nir_intrinsic_instr *intrin, const nir_address_format addr_format = nir_address_format_64bit_bounded_global; - assert(intrin->src[0].is_ssa); nir_ssa_def *desc_addr = nir_build_addr_iadd_imm( b, @@ -1488,7 +1478,6 @@ lower_image_size_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin, if (deref->deref_type != nir_deref_type_var) { assert(deref->deref_type == nir_deref_type_array); assert(nir_deref_instr_parent(deref)->deref_type == nir_deref_type_var); - assert(deref->arr.index.is_ssa); array_index = deref->arr.index.ssa; } else { array_index = nir_imm_int(b, 0); diff --git a/src/intel/vulkan/anv_nir_lower_multiview.c b/src/intel/vulkan/anv_nir_lower_multiview.c index 3ea2def2948..b46df4d7d6d 100644 --- a/src/intel/vulkan/anv_nir_lower_multiview.c +++ b/src/intel/vulkan/anv_nir_lower_multiview.c @@ -236,8 +236,6 @@ anv_nir_lower_multiview(nir_shader *shader, uint32_t view_mask, load->intrinsic != nir_intrinsic_load_view_index) continue; - assert(load->dest.is_ssa); - nir_ssa_def *value; if (load->intrinsic == nir_intrinsic_load_instance_id) { value = build_instance_id(&state); diff --git a/src/intel/vulkan_hasvk/anv_nir_apply_pipeline_layout.c b/src/intel/vulkan_hasvk/anv_nir_apply_pipeline_layout.c index 1133c33400d..2c8e63c5ff3 100644 --- a/src/intel/vulkan_hasvk/anv_nir_apply_pipeline_layout.c +++ b/src/intel/vulkan_hasvk/anv_nir_apply_pipeline_layout.c @@ -524,7 +524,6 @@ build_load_var_deref_descriptor_mem(nir_builder *b, nir_deref_instr *deref, if (deref->deref_type != nir_deref_type_var) { assert(deref->deref_type == nir_deref_type_array); assert(nir_deref_instr_parent(deref)->deref_type == nir_deref_type_var); - assert(deref->arr.index.is_ssa); array_index = deref->arr.index.ssa; } else { array_index = nir_imm_int(b, 0); @@ -563,7 +562,6 @@ build_res_index_for_chain(nir_builder *b, nir_intrinsic_instr *intrin, { if (intrin->intrinsic == nir_intrinsic_vulkan_resource_index) { b->cursor = nir_before_instr(&intrin->instr); - assert(intrin->src[0].is_ssa); *set = nir_intrinsic_desc_set(intrin); *binding = nir_intrinsic_binding(intrin); return build_res_index(b, *set, *binding, intrin->src[0].ssa, @@ -577,7 +575,6 @@ build_res_index_for_chain(nir_builder *b, nir_intrinsic_instr *intrin, b->cursor = nir_before_instr(&intrin->instr); - assert(intrin->src[1].is_ssa); return build_res_reindex(b, index, intrin->src[1].ssa, addr_format); } } @@ -715,7 +712,6 @@ lower_load_accel_struct_desc(nir_builder *b, /* Acceleration structure descriptors are always uint64_t */ nir_ssa_def *desc = build_load_descriptor_mem(b, desc_addr, 0, 1, 64, state); - assert(load_desc->dest.is_ssa); assert(load_desc->dest.ssa.bit_size == 64); assert(load_desc->dest.ssa.num_components == 1); nir_ssa_def_rewrite_uses(&load_desc->dest.ssa, desc); @@ -760,14 +756,12 @@ lower_res_index_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin, nir_address_format addr_format = addr_format_for_desc_type(nir_intrinsic_desc_type(intrin), state); - assert(intrin->src[0].is_ssa); nir_ssa_def *index = build_res_index(b, nir_intrinsic_desc_set(intrin), nir_intrinsic_binding(intrin), intrin->src[0].ssa, addr_format, state); - assert(intrin->dest.is_ssa); assert(intrin->dest.ssa.bit_size == index->bit_size); assert(intrin->dest.ssa.num_components == index->num_components); nir_ssa_def_rewrite_uses(&intrin->dest.ssa, index); @@ -791,7 +785,6 @@ lower_res_reindex_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin, intrin->src[1].ssa, addr_format); - assert(intrin->dest.is_ssa); assert(intrin->dest.ssa.bit_size == index->bit_size); assert(intrin->dest.ssa.num_components == index->num_components); nir_ssa_def_rewrite_uses(&intrin->dest.ssa, index); @@ -809,12 +802,10 @@ lower_load_vulkan_descriptor(nir_builder *b, nir_intrinsic_instr *intrin, const VkDescriptorType desc_type = nir_intrinsic_desc_type(intrin); nir_address_format addr_format = addr_format_for_desc_type(desc_type, state); - assert(intrin->src[0].is_ssa); nir_ssa_def *desc = build_buffer_addr_for_res_index(b, desc_type, intrin->src[0].ssa, addr_format, state); - assert(intrin->dest.is_ssa); assert(intrin->dest.ssa.bit_size == desc->bit_size); assert(intrin->dest.ssa.num_components == desc->num_components); nir_ssa_def_rewrite_uses(&intrin->dest.ssa, desc); @@ -835,7 +826,6 @@ lower_get_ssbo_size(nir_builder *b, nir_intrinsic_instr *intrin, nir_address_format addr_format = addr_format_for_desc_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER, state); - assert(intrin->src[0].is_ssa); nir_ssa_def *desc = build_buffer_addr_for_res_index(b, VK_DESCRIPTOR_TYPE_STORAGE_BUFFER, intrin->src[0].ssa, addr_format, state); diff --git a/src/intel/vulkan_hasvk/anv_nir_lower_multiview.c b/src/intel/vulkan_hasvk/anv_nir_lower_multiview.c index 6c9a545b6d2..16fae764a38 100644 --- a/src/intel/vulkan_hasvk/anv_nir_lower_multiview.c +++ b/src/intel/vulkan_hasvk/anv_nir_lower_multiview.c @@ -211,8 +211,6 @@ anv_nir_lower_multiview(nir_shader *shader, uint32_t view_mask) load->intrinsic != nir_intrinsic_load_view_index) continue; - assert(load->dest.is_ssa); - nir_ssa_def *value; if (load->intrinsic == nir_intrinsic_load_instance_id) { value = build_instance_id(&state); diff --git a/src/intel/vulkan_hasvk/anv_nir_lower_ycbcr_textures.c b/src/intel/vulkan_hasvk/anv_nir_lower_ycbcr_textures.c index f43aff91575..76b753829f1 100644 --- a/src/intel/vulkan_hasvk/anv_nir_lower_ycbcr_textures.c +++ b/src/intel/vulkan_hasvk/anv_nir_lower_ycbcr_textures.c @@ -125,7 +125,6 @@ create_plane_tex_instr_implicit(struct ycbcr_state *state, switch (old_tex->src[i].src_type) { case nir_tex_src_coord: if (plane_format->has_chroma && conversion->state.chroma_reconstruction) { - assert(old_tex->src[i].src.is_ssa); tex->src[i].src = nir_src_for_ssa(implicit_downsampled_coords(state, old_tex->src[i].src.ssa, diff --git a/src/mesa/state_tracker/st_nir_lower_builtin.c b/src/mesa/state_tracker/st_nir_lower_builtin.c index 9b3dc5c5d0e..cef41b42d4e 100644 --- a/src/mesa/state_tracker/st_nir_lower_builtin.c +++ b/src/mesa/state_tracker/st_nir_lower_builtin.c @@ -213,7 +213,6 @@ lower_builtin_instr(nir_builder *b, nir_instr *instr, UNUSED void *_data) def = nir_swizzle(b, def, swiz, intrin->num_components); /* and rewrite uses of original instruction: */ - assert(intrin->dest.is_ssa); nir_ssa_def_rewrite_uses(&intrin->dest.ssa, def); /* at this point intrin should be unused. We need to remove it diff --git a/src/microsoft/compiler/dxil_nir.c b/src/microsoft/compiler/dxil_nir.c index d9e64f1f35a..a1e40fa50b0 100644 --- a/src/microsoft/compiler/dxil_nir.c +++ b/src/microsoft/compiler/dxil_nir.c @@ -70,14 +70,12 @@ load_comps_to_vec(nir_builder *b, unsigned src_bit_size, static bool lower_32b_offset_load(nir_builder *b, nir_intrinsic_instr *intr, nir_variable *var) { - assert(intr->dest.is_ssa); unsigned bit_size = nir_dest_bit_size(intr->dest); unsigned num_components = nir_dest_num_components(intr->dest); unsigned num_bits = num_components * bit_size; b->cursor = nir_before_instr(&intr->instr); - assert(intr->src[0].is_ssa); nir_ssa_def *offset = intr->src[0].ssa; if (intr->intrinsic == nir_intrinsic_load_shared) offset = nir_iadd_imm(b, offset, nir_intrinsic_base(intr)); @@ -159,7 +157,6 @@ lower_masked_store_vec32(nir_builder *b, nir_ssa_def *offset, nir_ssa_def *index static bool lower_32b_offset_store(nir_builder *b, nir_intrinsic_instr *intr, nir_variable *var) { - assert(intr->src[0].is_ssa); unsigned num_components = nir_src_num_components(intr->src[0]); unsigned bit_size = nir_src_bit_size(intr->src[0]); unsigned num_bits = num_components * bit_size; @@ -622,7 +619,6 @@ lower_shared_atomic(nir_builder *b, nir_intrinsic_instr *intr, nir_variable *var { b->cursor = nir_before_instr(&intr->instr); - assert(intr->src[0].is_ssa); nir_ssa_def *offset = nir_iadd_imm(b, intr->src[0].ssa, nir_intrinsic_base(intr)); nir_ssa_def *index = nir_ushr_imm(b, offset, 2); @@ -860,8 +856,6 @@ upcast_phi_impl(nir_function_impl *impl, unsigned min_bit_size) nir_foreach_block_reverse(block, impl) { nir_foreach_phi_safe(phi, block) { - assert(phi->dest.is_ssa); - if (phi->dest.ssa.bit_size == 1 || phi->dest.ssa.bit_size >= min_bit_size) continue; @@ -1112,8 +1106,6 @@ lower_system_value_to_zero_filter(const nir_instr* instr, const void* cb_state) if (!nir_intrinsic_infos[intrin->intrinsic].has_dest) return false; - assert(intrin->dest.is_ssa); - zero_system_values_state* state = (zero_system_values_state*)cb_state; for (uint32_t i = 0; i < state->count; ++i) { gl_system_value value = state->values[i]; @@ -1818,7 +1810,6 @@ lower_kill(struct nir_builder *builder, nir_instr *instr, void *_cb_data) intr->intrinsic == nir_intrinsic_terminate) { nir_demote(builder); } else { - assert(intr->src[0].is_ssa); nir_demote_if(builder, intr->src[0].ssa); } @@ -2050,7 +2041,6 @@ split_unaligned_store(nir_builder *b, nir_intrinsic_instr *intrin, unsigned alig { enum gl_access_qualifier access = nir_intrinsic_access(intrin); - assert(intrin->src[1].is_ssa); nir_ssa_def *value = intrin->src[1].ssa; unsigned comp_size = value->bit_size / 8; unsigned num_comps = value->num_components; @@ -2106,10 +2096,8 @@ dxil_nir_split_unaligned_loads_stores(nir_shader *shader, nir_variable_mode mode nir_ssa_def *val; if (intrin->intrinsic == nir_intrinsic_load_deref) { - assert(intrin->dest.is_ssa); val = &intrin->dest.ssa; } else { - assert(intrin->src[1].is_ssa); val = intrin->src[1].ssa; } diff --git a/src/microsoft/compiler/dxil_nir_tess.c b/src/microsoft/compiler/dxil_nir_tess.c index 2a7e39bd314..4ed33ae8423 100644 --- a/src/microsoft/compiler/dxil_nir_tess.c +++ b/src/microsoft/compiler/dxil_nir_tess.c @@ -90,7 +90,6 @@ prune_patch_function_to_intrinsic_and_srcs(nir_function_impl *impl) nir_foreach_block(block, impl) { nir_if *following_if = nir_block_get_following_if(block); if (following_if) { - assert(following_if->condition.is_ssa); add_instr_and_srcs_to_set(instr_set, following_if->condition.ssa->parent_instr); } nir_foreach_instr_safe(instr, block) { diff --git a/src/microsoft/compiler/nir_to_dxil.c b/src/microsoft/compiler/nir_to_dxil.c index 46b96a88a3a..9844bc650b7 100644 --- a/src/microsoft/compiler/nir_to_dxil.c +++ b/src/microsoft/compiler/nir_to_dxil.c @@ -3129,7 +3129,6 @@ static bool emit_load_global_invocation_id(struct ntd_context *ctx, nir_intrinsic_instr *intr) { - assert(intr->dest.is_ssa); nir_component_mask_t comps = nir_ssa_def_components_read(&intr->dest.ssa); for (int i = 0; i < nir_intrinsic_dest_components(intr); i++) { @@ -3152,7 +3151,6 @@ static bool emit_load_local_invocation_id(struct ntd_context *ctx, nir_intrinsic_instr *intr) { - assert(intr->dest.is_ssa); nir_component_mask_t comps = nir_ssa_def_components_read(&intr->dest.ssa); for (int i = 0; i < nir_intrinsic_dest_components(intr); i++) { @@ -3175,8 +3173,6 @@ static bool emit_load_local_invocation_index(struct ntd_context *ctx, nir_intrinsic_instr *intr) { - assert(intr->dest.is_ssa); - const struct dxil_value *flattenedthreadidingroup = emit_flattenedthreadidingroup_call(ctx); if (!flattenedthreadidingroup) @@ -3190,7 +3186,6 @@ static bool emit_load_local_workgroup_id(struct ntd_context *ctx, nir_intrinsic_instr *intr) { - assert(intr->dest.is_ssa); nir_component_mask_t comps = nir_ssa_def_components_read(&intr->dest.ssa); for (int i = 0; i < nir_intrinsic_dest_components(intr); i++) { @@ -5136,7 +5131,6 @@ fixup_phi(struct ntd_context *ctx, nir_phi_instr *instr, for (unsigned i = 0; i < vphi->num_components; ++i) { size_t num_incoming = 0; nir_foreach_phi_src(src, instr) { - assert(src->src.is_ssa); const struct dxil_value *val = get_src_ssa(ctx, src->src.ssa, i); values[num_incoming] = val; blocks[num_incoming] = src->pred->index; diff --git a/src/nouveau/codegen/nv50_ir_from_nir.cpp b/src/nouveau/codegen/nv50_ir_from_nir.cpp index c32739e4081..8ca211af0bb 100644 --- a/src/nouveau/codegen/nv50_ir_from_nir.cpp +++ b/src/nouveau/codegen/nv50_ir_from_nir.cpp @@ -256,7 +256,6 @@ Converter::isResultSigned(nir_op op) DataType Converter::getDType(nir_alu_instr *insn) { - assert(insn->dest.dest.is_ssa); return getDType(insn->op, insn->dest.dest.ssa.bit_size); } @@ -281,7 +280,6 @@ Converter::getDType(nir_intrinsic_instr *insn) break; } - assert(insn->dest.is_ssa); return typeOfSize(insn->dest.ssa.bit_size / 8, isFloat, isSigned); } @@ -319,7 +317,6 @@ Converter::getSTypes(nir_alu_instr *insn) DataType Converter::getSType(nir_src &src, bool isFloat, bool isSigned) { - assert(src.is_ssa); const uint8_t bitSize = src.ssa->bit_size; DataType ty = typeOfSize(bitSize / 8, isFloat, isSigned); diff --git a/src/panfrost/compiler/bi_lower_divergent_indirects.c b/src/panfrost/compiler/bi_lower_divergent_indirects.c index d8b7d3ec1b5..3c50fb2211e 100644 --- a/src/panfrost/compiler/bi_lower_divergent_indirects.c +++ b/src/panfrost/compiler/bi_lower_divergent_indirects.c @@ -99,7 +99,6 @@ bi_lower_divergent_indirects_impl(nir_builder *b, nir_instr *instr, void *data) nir_pop_if(b, NULL); if (has_dest) { - assert(c_intr->dest.is_ssa); nir_ssa_def *c_ssa = &c_intr->dest.ssa; res = nir_if_phi(b, c_ssa, res); } diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c index 9d0e0949813..eb8a4426100 100644 --- a/src/panfrost/midgard/midgard_compile.c +++ b/src/panfrost/midgard/midgard_compile.c @@ -231,7 +231,6 @@ midgard_nir_lower_global_load_instr(nir_builder *b, nir_instr *instr, b->cursor = nir_before_instr(instr); - assert(intr->src[0].is_ssa); nir_ssa_def *addr = intr->src[0].ssa; nir_ssa_def *comps[MIR_VEC_COMPONENTS]; @@ -1553,7 +1552,6 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr) * up with unconsumed load_register instructions. Translate them here. 99% * of the time, these moves will be DCE'd away. */ - assert(instr->src[0].is_ssa); nir_ssa_def *handle = instr->src[0].ssa; midgard_instruction ins = diff --git a/src/panfrost/midgard/midgard_nir_type_csel.c b/src/panfrost/midgard/midgard_nir_type_csel.c index 3cf6e1546df..e9bca6157d5 100644 --- a/src/panfrost/midgard/midgard_nir_type_csel.c +++ b/src/panfrost/midgard/midgard_nir_type_csel.c @@ -19,7 +19,6 @@ pass(nir_builder *b, nir_instr *instr, void *data) return false; BITSET_WORD *float_types = data; - assert(alu->dest.dest.is_ssa); if (BITSET_TEST(float_types, alu->dest.dest.ssa.index)) { alu->op = nir_op_b32fcsel_mdg; return true; diff --git a/src/panfrost/util/pan_lower_64bit_intrin.c b/src/panfrost/util/pan_lower_64bit_intrin.c index 3730e7660c8..989e4ab9159 100644 --- a/src/panfrost/util/pan_lower_64bit_intrin.c +++ b/src/panfrost/util/pan_lower_64bit_intrin.c @@ -57,7 +57,6 @@ nir_lower_64bit_intrin_instr(nir_builder *b, nir_instr *instr, void *data) b->cursor = nir_after_instr(instr); - assert(intr->dest.is_ssa); intr->dest.ssa.bit_size = 32; nir_ssa_def *conv = nir_u2u64(b, &intr->dest.ssa); diff --git a/src/panfrost/vulkan/panvk_vX_nir_lower_descriptors.c b/src/panfrost/vulkan/panvk_vX_nir_lower_descriptors.c index f1f9cc33866..034d861bdfd 100644 --- a/src/panfrost/vulkan/panvk_vX_nir_lower_descriptors.c +++ b/src/panfrost/vulkan/panvk_vX_nir_lower_descriptors.c @@ -256,7 +256,6 @@ lower_res_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin, nir_ssa_def *res; switch (intrin->intrinsic) { case nir_intrinsic_vulkan_resource_index: - assert(intrin->src[0].is_ssa); res = build_res_index(b, nir_intrinsic_desc_set(intrin), nir_intrinsic_binding(intrin), intrin->src[0].ssa, addr_format, ctx); @@ -269,7 +268,6 @@ lower_res_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin, break; case nir_intrinsic_load_vulkan_descriptor: - assert(intrin->src[0].is_ssa); res = build_buffer_addr_for_res_index(b, intrin->src[0].ssa, addr_format, ctx); break; @@ -278,7 +276,6 @@ lower_res_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin, unreachable("Unhandled resource intrinsic"); } - assert(intrin->dest.is_ssa); assert(intrin->dest.ssa.bit_size == res->bit_size); assert(intrin->dest.ssa.num_components == res->num_components); nir_ssa_def_rewrite_uses(&intrin->dest.ssa, res); @@ -296,7 +293,6 @@ get_resource_deref_binding(nir_deref_instr *deref, uint32_t *set, *index_ssa = NULL; if (deref->deref_type == nir_deref_type_array) { - assert(deref->arr.index.is_ssa); if (index_imm != NULL && nir_src_is_const(deref->arr.index)) *index_imm = nir_src_as_uint(deref->arr.index); else @@ -506,8 +502,6 @@ lower_img_intrinsic(nir_builder *b, nir_intrinsic_instr *intr, if (intr->intrinsic == nir_intrinsic_image_deref_size || intr->intrinsic == nir_intrinsic_image_deref_samples) { - assert(intr->dest.is_ssa); - const enum glsl_sampler_dim dim = nir_intrinsic_image_dim(intr); nir_ssa_def *res; diff --git a/src/vulkan/runtime/vk_nir_convert_ycbcr.c b/src/vulkan/runtime/vk_nir_convert_ycbcr.c index 9e0f1718aae..27d971db107 100644 --- a/src/vulkan/runtime/vk_nir_convert_ycbcr.c +++ b/src/vulkan/runtime/vk_nir_convert_ycbcr.c @@ -245,7 +245,6 @@ create_plane_tex_instr_implicit(struct ycbcr_state *state, switch (old_tex->src[i].src_type) { case nir_tex_src_coord: if (format_plane->has_chroma && conversion->chroma_reconstruction) { - assert(old_tex->src[i].src.is_ssa); tex->src[i].src = nir_src_for_ssa(implicit_downsampled_coords(state, old_tex->src[i].src.ssa,