nir: Make the load_store_vectorizer provide align_mul + align_offset.

It was passing an encoding of the two that wasn't good for ensuring "Don't
combine loads that would make us straddle a vec4 boundary" for
nir_lower_ubo_vec4.

Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6612>

src/amd/compiler/aco_instruction_selection_setup.cpp

@@ -383,7 +383,8 @@ type_size(const struct glsl_type *type, bool bindless)
 }
 
 bool
-mem_vectorize_callback(unsigned align, unsigned bit_size,
+mem_vectorize_callback(unsigned align_mul, unsigned align_offset,
+                       unsigned bit_size,
                        unsigned num_components, unsigned high_offset,
                        nir_intrinsic_instr *low, nir_intrinsic_instr *high)
 {
@@ -394,6 +395,12 @@ mem_vectorize_callback(unsigned align, unsigned bit_size,
    if (bit_size * num_components > 128)
       return false;
 
+   uint32_t align;
+   if (align_offset)
+      align = 1 << (ffs(align_offset) - 1);
+   else
+      align = align_mul;
+
    switch (low->intrinsic) {
    case nir_intrinsic_load_global:
    case nir_intrinsic_store_global: