From 5ebb014bdf87257abed3d3401a3074b82da84335 Mon Sep 17 00:00:00 2001 From: Georg Lehmann Date: Sat, 4 Jun 2022 21:26:45 +0200 Subject: [PATCH] radv, aco: Round texture array layer in NIR. Foz-DB Navi21: Totals from 9100 (6.75% of 134913) affected shaders: VGPRs: 609912 -> 610104 (+0.03%); split: -0.01%, +0.05% SpillSGPRs: 1459 -> 1489 (+2.06%) CodeSize: 66705920 -> 66620288 (-0.13%); split: -0.13%, +0.00% MaxWaves: 148546 -> 148518 (-0.02%); split: +0.00%, -0.02% Instrs: 12278485 -> 12255821 (-0.18%); split: -0.19%, +0.00% Latency: 277414916 -> 277261192 (-0.06%); split: -0.08%, +0.02% InvThroughput: 48431180 -> 48394637 (-0.08%); split: -0.11%, +0.03% VClause: 250866 -> 251062 (+0.08%); split: -0.04%, +0.11% SClause: 498377 -> 498173 (-0.04%); split: -0.08%, +0.04% Copies: 652835 -> 655371 (+0.39%); split: -0.09%, +0.48% Branches: 284367 -> 284371 (+0.00%); split: -0.00%, +0.00% PreSGPRs: 498580 -> 498477 (-0.02%) PreVGPRs: 558436 -> 558709 (+0.05%); split: -0.01%, +0.06% Signed-off-by: Georg Lehmann Reviewed-by: Rhys Perry Part-of: --- .../compiler/aco_instruction_selection.cpp | 22 +++---------------- src/amd/vulkan/radv_shader.c | 1 + 2 files changed, 4 insertions(+), 19 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 0176c994e6d..bd027fadda6 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -9169,13 +9169,9 @@ prepare_cube_coords(isel_context* ctx, std::vector& coords, Temp* ddx, Tem aco_opcode madmk = ctx->program->gfx_level >= GFX10_3 ? aco_opcode::v_fmamk_f32 : aco_opcode::v_madmk_f32; - if (is_array) { - coords[3] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[3]); - - /* see comment in ac_prepare_cube_coords() */ - if (ctx->options->gfx_level <= GFX8) - coords[3] = bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand::zero(), coords[3]); - } + /* see comment in ac_prepare_cube_coords() */ + if (is_array && ctx->options->gfx_level <= GFX8) + coords[3] = bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand::zero(), coords[3]); ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), coords[0], coords[1], coords[2]); @@ -9425,18 +9421,6 @@ visit_tex(isel_context* ctx, nir_tex_instr* instr) has_derivs = true; } - if (instr->coord_components > 1 && instr->sampler_dim == GLSL_SAMPLER_DIM_1D && - instr->is_array && instr->op != nir_texop_txf) - coords[1] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[1]); - - if (instr->coord_components > 2 && - (instr->sampler_dim == GLSL_SAMPLER_DIM_2D || instr->sampler_dim == GLSL_SAMPLER_DIM_MS || - instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS || - instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) && - instr->is_array && instr->op != nir_texop_txf && instr->op != nir_texop_fragment_fetch_amd && - instr->op != nir_texop_fragment_mask_fetch_amd) - coords[2] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[2]); - if (ctx->options->gfx_level == GFX9 && instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->op != nir_texop_lod && instr->coord_components) { assert(coords.size() > 0 && coords.size() < 3); diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index a0233ef4df7..4dc180f8616 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -827,6 +827,7 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_pipeline_ .lower_to_fragment_fetch_amd = true, .lower_lod_zero_width = true, .lower_invalid_implicit_lod = true, + .lower_array_layer_round_even = true, }; NIR_PASS(_, nir, nir_lower_tex, &tex_options);