From 5e6e47ecea863ea044bff6256934251b54e12a83 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20Sch=C3=BCrmann?= Date: Wed, 16 Mar 2022 17:25:35 +0100 Subject: [PATCH] aco/ra: improve split_vector register assignment if the operand is not killed This allows for more coalescing when lowering the copies. Totals from 44801 (33.21% of 134913) affected shaders: (GFX10.3) VGPRs: 1513264 -> 1513248 (-0.00%) CodeSize: 113354240 -> 113172872 (-0.16%); split: -0.16%, +0.00% Instrs: 21648793 -> 21603397 (-0.21%); split: -0.21%, +0.00% Latency: 95762290 -> 95757403 (-0.01%); split: -0.01%, +0.00% InvThroughput: 15427354 -> 15427341 (-0.00%); split: -0.00%, +0.00% Copies: 2065330 -> 2019933 (-2.20%); split: -2.20%, +0.00% Reviewed-by: Rhys Perry Part-of: --- src/amd/compiler/aco_register_allocation.cpp | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp index 108dfd04b8c..bd3f1cb525f 100644 --- a/src/amd/compiler/aco_register_allocation.cpp +++ b/src/amd/compiler/aco_register_allocation.cpp @@ -2793,10 +2793,24 @@ register_allocation(Program* program, std::vector& live_out_per_block, ra /* find free reg */ if (instr->opcode == aco_opcode::p_split_vector) { PhysReg reg = instr->operands[0].physReg(); + RegClass rc = definition->regClass(); for (unsigned j = 0; j < i; j++) reg.reg_b += instr->definitions[j].bytes(); - if (get_reg_specified(ctx, register_file, definition->regClass(), instr, reg)) + if (get_reg_specified(ctx, register_file, rc, instr, reg)) { definition->setFixed(reg); + } else if (i == 0) { + RegClass vec_rc = RegClass::get(rc.type(), instr->operands[0].bytes()); + DefInfo info(ctx, ctx.pseudo_dummy, vec_rc, -1); + std::pair res = get_reg_simple(ctx, register_file, info); + reg = res.first; + if (res.second && get_reg_specified(ctx, register_file, rc, instr, reg)) + definition->setFixed(reg); + } else if (instr->definitions[i - 1].isFixed()) { + reg = instr->definitions[i - 1].physReg(); + reg.reg_b += instr->definitions[i - 1].bytes(); + if (get_reg_specified(ctx, register_file, rc, instr, reg)) + definition->setFixed(reg); + } } else if (instr->opcode == aco_opcode::p_wqm || instr->opcode == aco_opcode::p_parallelcopy) { PhysReg reg = instr->operands[i].physReg();