diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 82f6b0df525..e60da86d0e6 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -411,6 +411,28 @@ uint32_t ac_memory_ops_per_clock(uint32_t vram_type);
 
 uint32_t ac_gfx103_get_cu_mask_ps(const struct radeon_info *info);
 
+/* Number of entries in the mesh shader scratch ring.
+ * This depends on VGT_GS_MAX_WAVE_ID which is set by the kernel
+ * and is impossible to query. We leave it on its maximum value
+ * because real applications are unlikely to use it.
+ *
+ * The maximum ID on GFX10.3 is 2047 (0x7ff), so we need 2048 entries.
+ */
+#define AC_MESH_SCRATCH_NUM_ENTRIES 2048
+
+/* Size of each entry in the mesh shader scratch ring.
+ * We must ensure that the absolute maximum mesh shader output fits here.
+ *
+ * Mesh shaders can create up to 256 vertices/primitives per workgroup,
+ * and up to the following amount of outputs:
+ * - 32 parameters
+ * - 4 positions (clip/cull distance, etc.)
+ * - 4 per-primitive built-in outputs (layer, view index, prim id, VRS rate)
+ * - primitive indices which are always kept in LDS
+ * That is a total of 32+4+4=40 output slots x 16 bytes per slot x 256 = 160K bytes.
+ */
+#define AC_MESH_SCRATCH_ENTRY_BYTES (160 * 1024)
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/amd/vulkan/nir/radv_nir_lower_abi.c b/src/amd/vulkan/nir/radv_nir_lower_abi.c
index 381a0b95d9c..bad2209020f 100644
--- a/src/amd/vulkan/nir/radv_nir_lower_abi.c
+++ b/src/amd/vulkan/nir/radv_nir_lower_abi.c
@@ -210,7 +210,7 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state)
    case nir_intrinsic_load_ring_mesh_scratch_offset_amd:
       /* gs_tg_info[0:11] is ordered_wave_id. Multiply by the ring entry size. */
       replacement = nir_imul_imm(b, nir_iand_imm(b, ac_nir_load_arg(b, &s->args->ac, s->args->ac.gs_tg_info), 0xfff),
-                                 RADV_MESH_SCRATCH_ENTRY_BYTES);
+                                 AC_MESH_SCRATCH_ENTRY_BYTES);
       break;
    case nir_intrinsic_load_lshs_vertex_stride_amd: {
       if (stage == MESA_SHADER_VERTEX) {
diff --git a/src/amd/vulkan/radv_constants.h b/src/amd/vulkan/radv_constants.h
index 0511de49949..4c5014b2edb 100644
--- a/src/amd/vulkan/radv_constants.h
+++ b/src/amd/vulkan/radv_constants.h
@@ -80,28 +80,6 @@
  */
 #define RADV_MAX_MEMORY_ALLOCATION_SIZE 0xFFFFFFFCull
 
-/* Number of entries in the mesh shader scratch ring.
- * This depends on VGT_GS_MAX_WAVE_ID which is set by the kernel
- * and is impossible to query. We leave it on its maximum value
- * because real applications are unlikely to use it.
- *
- * The maximum ID on GFX10.3 is 2047 (0x7ff), so we need 2048 entries.
- */
-#define RADV_MESH_SCRATCH_NUM_ENTRIES 2048
-
-/* Size of each entry in the mesh shader scratch ring.
- * We must ensure that the absolute maximum mesh shader output fits here.
- *
- * Mesh shaders can create up to 256 vertices/primitives per workgroup,
- * and up to the following amount of outputs:
- * - 32 parameters
- * - 4 positions (clip/cull distance, etc.)
- * - 4 per-primitive built-in outputs (layer, view index, prim id, VRS rate)
- * - primitive indices which are always kept in LDS
- * That is a total of 32+4+4=40 output slots x 16 bytes per slot x 256 = 160K bytes.
- */
-#define RADV_MESH_SCRATCH_ENTRY_BYTES (160 * 1024)
-
 /* Number of invocations in each subgroup. */
 #define RADV_SUBGROUP_SIZE 64
 
diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c
index c3b0f864f89..25bdd2bd665 100644
--- a/src/amd/vulkan/radv_queue.c
+++ b/src/amd/vulkan/radv_queue.c
@@ -334,7 +334,7 @@ radv_fill_shader_rings(struct radv_device *device, uint32_t *desc, struct radeon
    desc += 8;
 
    if (mesh_scratch_ring_bo) {
-      radv_set_ring_buffer(pdev, mesh_scratch_ring_bo, 0, RADV_MESH_SCRATCH_NUM_ENTRIES * RADV_MESH_SCRATCH_ENTRY_BYTES,
+      radv_set_ring_buffer(pdev, mesh_scratch_ring_bo, 0, AC_MESH_SCRATCH_NUM_ENTRIES * AC_MESH_SCRATCH_ENTRY_BYTES,
                            false, false, false, 0, 0, &desc[0]);
    }
 
@@ -1043,13 +1043,13 @@ radv_update_preamble_cs(struct radv_queue_state *queue, struct radv_device *devi
    if (!queue->ring_info.mesh_scratch_ring && needs->mesh_scratch_ring) {
       assert(pdev->info.gfx_level >= GFX10_3);
       result =
-         radv_bo_create(device, NULL, RADV_MESH_SCRATCH_NUM_ENTRIES * RADV_MESH_SCRATCH_ENTRY_BYTES, 256,
+         radv_bo_create(device, NULL, AC_MESH_SCRATCH_NUM_ENTRIES * AC_MESH_SCRATCH_ENTRY_BYTES, 256,
                         RADEON_DOMAIN_VRAM, ring_bo_flags, RADV_BO_PRIORITY_SCRATCH, 0, true, &mesh_scratch_ring_bo);
 
       if (result != VK_SUCCESS)
          goto fail;
       radv_rmv_log_command_buffer_bo_create(device, mesh_scratch_ring_bo, 0, 0,
-                                            RADV_MESH_SCRATCH_NUM_ENTRIES * RADV_MESH_SCRATCH_ENTRY_BYTES);
+                                            AC_MESH_SCRATCH_NUM_ENTRIES * AC_MESH_SCRATCH_ENTRY_BYTES);
    }
 
    if (!queue->ring_info.ge_rings && needs->ge_rings) {