diff --git a/src/freedreno/common/freedreno_stompable_regs.h b/src/freedreno/common/freedreno_stompable_regs.h
index d92704e0052..6e8a7cacc7d 100644
--- a/src/freedreno/common/freedreno_stompable_regs.h
+++ b/src/freedreno/common/freedreno_stompable_regs.h
@@ -61,6 +61,13 @@ fd_reg_stomp_allowed(chip CHIP, uint16_t reg)
        * certain debug register between BR/BV. This one causes GPU to hang.
        */
       case REG_A7XX_SP_UNKNOWN_AE73:
+      case REG_A7XX_RB_UNKNOWN_8E79:
+      case REG_A7XX_SP_UNKNOWN_AE09:
+      case REG_A6XX_TPL1_UNKNOWN_B602:
+         return false;
+      case REG_A7XX_SP_GS_VGPR_CONFIG:
+      case REG_A7XX_SP_FS_VGPR_CONFIG:
+      case REG_A7XX_SP_CS_VGPR_CONFIG:
          return false;
       }
       break;
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index eeda3fae1ac..3e5e3473967 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -2189,7 +2189,7 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x80a5" name="GRAS_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/>
 	<reg32 offset="0x80a6" name="GRAS_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/>
 
-	<reg32 offset="0x80a7" name="GRAS_UNKNOWN_80A7" variants="A7XX-" usage="rp_blit"/>
+	<reg32 offset="0x80a7" name="GRAS_UNKNOWN_80A7" variants="A7XX-" usage="cmd"/>
 
 	<!-- 0x80a7-0x80ae invalid -->
 	<reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF" pos="0" usage="cmd"/>
@@ -2322,7 +2322,7 @@ to upconvert to 32b float internally?
 		<bitfield name="BASE_MIP_LEVEL" low="28" high="31" type="uint"/>
 	</reg32>
 
-	<reg32 offset="0x810b" name="GRAS_UNKNOWN_810B" variants="A7XX-" usage="rp_blit"/>
+	<reg32 offset="0x810b" name="GRAS_UNKNOWN_810B" variants="A7XX-" usage="cmd"/>
 
 	<!-- 0x810c-0x810f invalid -->
 
@@ -2787,7 +2787,7 @@ to upconvert to 32b float internally?
 		<value value="0x2" name="CCU_CACHE_SIZE_QUARTER"/>
 		<value value="0x3" name="CCU_CACHE_SIZE_EIGHTH"/>
 	</enum>
-	<reg32 offset="0x88e5" name="RB_CCU_CNTL2" variants="A7XX-" usage="rp_blit">
+	<reg32 offset="0x88e5" name="RB_CCU_CNTL2" variants="A7XX-" usage="cmd">
 		<bitfield name="DEPTH_OFFSET_HI" pos="0" type="hex"/>
 		<bitfield name="COLOR_OFFSET_HI" pos="2" type="hex"/>
 		<bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/>