From 5d265257a052670b2a4c73b2b524158c94ecc9f8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20Sch=C3=BCrmann?= Date: Tue, 19 Mar 2024 15:21:00 +0100 Subject: [PATCH] aco: remove SOPP_instruction::block member Re-use SOPP_instruction::imm instead. Part-of: --- src/amd/compiler/aco_assembler.cpp | 16 +++++----- src/amd/compiler/aco_form_hard_clauses.cpp | 2 +- src/amd/compiler/aco_insert_NOPs.cpp | 29 +++++++++---------- src/amd/compiler/aco_insert_waitcnt.cpp | 2 -- .../compiler/aco_instruction_selection.cpp | 22 +++++++------- src/amd/compiler/aco_ir.cpp | 4 +-- src/amd/compiler/aco_ir.h | 6 ++-- src/amd/compiler/aco_lower_to_hw_instr.cpp | 19 ++++++------ src/amd/compiler/aco_opcodes.py | 3 +- src/amd/compiler/aco_print_ir.cpp | 6 ++-- src/amd/compiler/tests/test_assembler.cpp | 12 ++++---- src/amd/compiler/tests/test_insert_nops.cpp | 24 +++++++-------- 12 files changed, 71 insertions(+), 74 deletions(-) diff --git a/src/amd/compiler/aco_assembler.cpp b/src/amd/compiler/aco_assembler.cpp index 768f995b0fa..1deb8b931cd 100644 --- a/src/amd/compiler/aco_assembler.cpp +++ b/src/amd/compiler/aco_assembler.cpp @@ -220,6 +220,7 @@ emit_sopp_instruction(asm_context& ctx, std::vector& out, Instruction* sopp.pass_flags = 0; ctx.branches.emplace_back(out.size(), &sopp); } else { + assert(sopp.imm <= UINT16_MAX); encoding |= (uint16_t)sopp.imm; } out.push_back(encoding); @@ -1301,8 +1302,7 @@ fix_branches_gfx10(asm_context& ctx, std::vector& out) auto buggy_branch_it = std::find_if( ctx.branches.begin(), ctx.branches.end(), [&ctx](const auto& branch) -> bool { - return ((int)ctx.program->blocks[branch.second->block].offset - branch.first - 1) == - 0x3f; + return ((int)ctx.program->blocks[branch.second->imm].offset - branch.first - 1) == 0x3f; }); gfx10_3f_bug = buggy_branch_it != ctx.branches.end(); @@ -1323,7 +1323,7 @@ emit_long_jump(asm_context& ctx, SOPP_instruction* branch, bool backwards, Definition def; if (branch->definitions.empty()) { - assert(ctx.program->blocks[branch->block].kind & block_kind_discard_early_exit); + assert(ctx.program->blocks[branch->imm].kind & block_kind_discard_early_exit); def = Definition(PhysReg(0), s2); /* The discard early exit block doesn't use SGPRs. */ } else { def = branch->definitions[0]; @@ -1348,7 +1348,7 @@ emit_long_jump(asm_context& ctx, SOPP_instruction* branch, bool backwards, case aco_opcode::s_cbranch_execnz: inv = aco_opcode::s_cbranch_execz; break; default: unreachable("Unhandled long jump."); } - instr.reset(bld.sopp(inv, -1, 6)); + instr.reset(bld.sopp(inv, 6)); emit_sopp_instruction(ctx, out, instr.get(), true); } @@ -1385,11 +1385,11 @@ fix_branches(asm_context& ctx, std::vector& out) fix_branches_gfx10(ctx, out); for (std::pair& branch : ctx.branches) { - int offset = (int)ctx.program->blocks[branch.second->block].offset - branch.first - 1; + int offset = (int)ctx.program->blocks[branch.second->imm].offset - branch.first - 1; if ((offset < INT16_MIN || offset > INT16_MAX) && !branch.second->pass_flags) { std::vector long_jump; bool backwards = - ctx.program->blocks[branch.second->block].offset < (unsigned)branch.first; + ctx.program->blocks[branch.second->imm].offset < (unsigned)branch.first; emit_long_jump(ctx, branch.second, backwards, long_jump); out[branch.first] = long_jump[0]; @@ -1401,7 +1401,7 @@ fix_branches(asm_context& ctx, std::vector& out) if (branch.second->pass_flags) { int after_getpc = branch.first + branch.second->pass_flags - 2; - offset = (int)ctx.program->blocks[branch.second->block].offset - after_getpc; + offset = (int)ctx.program->blocks[branch.second->imm].offset - after_getpc; out[branch.first + branch.second->pass_flags - 1] = offset * 4; } else { out[branch.first] &= 0xffff0000u; @@ -1456,7 +1456,7 @@ align_block(asm_context& ctx, std::vector& code, Block& block) if (change_prefetch) { Builder bld(ctx.program); int16_t prefetch_mode = loop_num_cl == 3 ? 0x1 : 0x2; - aco_ptr instr(bld.sopp(aco_opcode::s_inst_prefetch, -1, prefetch_mode)); + aco_ptr instr(bld.sopp(aco_opcode::s_inst_prefetch, prefetch_mode)); emit_instruction(ctx, nops, instr.get()); insert_code(ctx, code, loop_header->offset, nops.size(), nops.data()); diff --git a/src/amd/compiler/aco_form_hard_clauses.cpp b/src/amd/compiler/aco_form_hard_clauses.cpp index 66f0ded6f8d..60b1e00a6bb 100644 --- a/src/amd/compiler/aco_form_hard_clauses.cpp +++ b/src/amd/compiler/aco_form_hard_clauses.cpp @@ -68,7 +68,7 @@ emit_clause(Builder& bld, unsigned num_instrs, aco_ptr* instrs) unsigned clause_size = end - start; if (clause_size > 1) - bld.sopp(aco_opcode::s_clause, -1, clause_size - 1); + bld.sopp(aco_opcode::s_clause, clause_size - 1); for (unsigned i = start; i < num_instrs; i++) bld.insert(std::move(instrs[i])); diff --git a/src/amd/compiler/aco_insert_NOPs.cpp b/src/amd/compiler/aco_insert_NOPs.cpp index 52ec359fa6e..82c37aac21e 100644 --- a/src/amd/compiler/aco_insert_NOPs.cpp +++ b/src/amd/compiler/aco_insert_NOPs.cpp @@ -614,7 +614,6 @@ handle_instruction_gfx6(State& state, NOP_ctx_gfx6& ctx, aco_ptr& i aco_ptr nop{ create_instruction(aco_opcode::s_nop, Format::SOPP, 0, 0)}; nop->imm = NOPs - 1; - nop->block = -1; new_instructions.emplace_back(std::move(nop)); } @@ -784,7 +783,7 @@ resolve_all_gfx6(State& state, NOP_ctx_gfx6& ctx, ctx.add_wait_states(NOPs); if (NOPs) { Builder bld(state.program, &new_instructions); - bld.sopp(aco_opcode::s_nop, -1, NOPs - 1); + bld.sopp(aco_opcode::s_nop, NOPs - 1); } } @@ -897,7 +896,7 @@ handle_instruction_gfx10(State& state, NOP_ctx_gfx10& ctx, aco_ptr& unsigned vm_vsrc = 7; unsigned sa_sdst = 1; if (debug_flags & DEBUG_FORCE_WAITDEPS) { - bld.sopp(aco_opcode::s_waitcnt_depctr, -1, 0x0000); + bld.sopp(aco_opcode::s_waitcnt_depctr, 0x0000); vm_vsrc = 0; sa_sdst = 0; } else if (instr->opcode == aco_opcode::s_waitcnt_depctr) { @@ -941,7 +940,7 @@ handle_instruction_gfx10(State& state, NOP_ctx_gfx10& ctx, aco_ptr& ctx.sgprs_read_by_VMEM_store.reset(); /* Insert s_waitcnt_depctr instruction with magic imm to mitigate the problem */ - bld.sopp(aco_opcode::s_waitcnt_depctr, -1, 0xffe3); + bld.sopp(aco_opcode::s_waitcnt_depctr, 0xffe3); } } else if (instr->isVALU()) { /* Hazard is mitigated by any VALU instruction */ @@ -977,7 +976,7 @@ handle_instruction_gfx10(State& state, NOP_ctx_gfx10& ctx, aco_ptr& ctx.has_nonVALU_exec_read = false; /* Insert s_waitcnt_depctr instruction with magic imm to mitigate the problem */ - bld.sopp(aco_opcode::s_waitcnt_depctr, -1, 0xfffe); + bld.sopp(aco_opcode::s_waitcnt_depctr, 0xfffe); } else if (instr_writes_sgpr(instr)) { /* Any VALU instruction that writes an SGPR mitigates the problem */ ctx.has_nonVALU_exec_read = false; @@ -1052,7 +1051,7 @@ handle_instruction_gfx10(State& state, NOP_ctx_gfx10& ctx, aco_ptr& if (instr->isMUBUF() || instr->isMTBUF()) { uint32_t offset = instr->isMUBUF() ? instr->mubuf().offset : instr->mtbuf().offset; if (offset & 6) - bld.sopp(aco_opcode::s_nop, -1, 0); + bld.sopp(aco_opcode::s_nop, 0); } } @@ -1064,7 +1063,7 @@ handle_instruction_gfx10(State& state, NOP_ctx_gfx10& ctx, aco_ptr& } else if (ctx.has_writelane) { ctx.has_writelane = false; if (instr->isMIMG() && get_mimg_nsa_dwords(instr.get()) > 0) - bld.sopp(aco_opcode::s_nop, -1, 0); + bld.sopp(aco_opcode::s_nop, 0); } } @@ -1105,7 +1104,7 @@ resolve_all_gfx10(State& state, NOP_ctx_gfx10& ctx, } if (waitcnt_depctr != 0xffff) - bld.sopp(aco_opcode::s_waitcnt_depctr, -1, waitcnt_depctr); + bld.sopp(aco_opcode::s_waitcnt_depctr, waitcnt_depctr); /* SMEMtoVectorWriteHazard */ if (ctx.sgprs_read_by_SMEM.any()) { @@ -1124,7 +1123,7 @@ resolve_all_gfx10(State& state, NOP_ctx_gfx10& ctx, ctx.has_NSA_MIMG = ctx.has_writelane = false; /* Any instruction resolves these hazards. */ if (new_instructions.size() == prev_count) - bld.sopp(aco_opcode::s_nop, -1, 0); + bld.sopp(aco_opcode::s_nop, 0); } } @@ -1412,7 +1411,7 @@ handle_instruction_gfx11(State& state, NOP_ctx_gfx11& ctx, aco_ptr& unsigned sa_sdst = 1; if (debug_flags & DEBUG_FORCE_WAITDEPS) { - bld.sopp(aco_opcode::s_waitcnt_depctr, -1, 0x0000); + bld.sopp(aco_opcode::s_waitcnt_depctr, 0x0000); va_vdst = 0; vm_vsrc = 0; sa_sdst = 0; @@ -1447,13 +1446,13 @@ handle_instruction_gfx11(State& state, NOP_ctx_gfx11& ctx, aco_ptr& } } if (num_trans <= 1 && num_valu <= 5) { - bld.sopp(aco_opcode::s_waitcnt_depctr, -1, 0x0fff); + bld.sopp(aco_opcode::s_waitcnt_depctr, 0x0fff); va_vdst = 0; } } if (va_vdst > 0 && handle_valu_partial_forwarding_hazard(state, instr)) { - bld.sopp(aco_opcode::s_waitcnt_depctr, -1, 0x0fff); + bld.sopp(aco_opcode::s_waitcnt_depctr, 0x0fff); va_vdst = 0; } @@ -1466,7 +1465,7 @@ handle_instruction_gfx11(State& state, NOP_ctx_gfx11& ctx, aco_ptr& ctx.sgpr_read_by_valu_as_lanemask.reset(); } else if (state.program->wave_size == 64 && instr->isSALU() && check_read_regs(instr, ctx.sgpr_read_by_valu_as_lanemask_then_wr_by_salu)) { - bld.sopp(aco_opcode::s_waitcnt_depctr, -1, 0xfffe); + bld.sopp(aco_opcode::s_waitcnt_depctr, 0xfffe); sa_sdst = 0; } @@ -1552,7 +1551,7 @@ handle_instruction_gfx11(State& state, NOP_ctx_gfx11& ctx, aco_ptr& if (ctx.vgpr_used_by_vmem_load[instr->definitions[0].physReg().reg() - 256] || ctx.vgpr_used_by_vmem_store[instr->definitions[0].physReg().reg() - 256] || ctx.vgpr_used_by_ds[instr->definitions[0].physReg().reg() - 256]) { - bld.sopp(aco_opcode::s_waitcnt_depctr, -1, 0xffe3); + bld.sopp(aco_opcode::s_waitcnt_depctr, 0xffe3); ctx.vgpr_used_by_vmem_load.reset(); ctx.vgpr_used_by_vmem_store.reset(); ctx.vgpr_used_by_ds.reset(); @@ -1634,7 +1633,7 @@ resolve_all_gfx11(State& state, NOP_ctx_gfx11& ctx, } if (waitcnt_depctr != 0xffff) - bld.sopp(aco_opcode::s_waitcnt_depctr, -1, waitcnt_depctr); + bld.sopp(aco_opcode::s_waitcnt_depctr, waitcnt_depctr); } template diff --git a/src/amd/compiler/aco_insert_waitcnt.cpp b/src/amd/compiler/aco_insert_waitcnt.cpp index 0209f44c377..af89ad48e29 100644 --- a/src/amd/compiler/aco_insert_waitcnt.cpp +++ b/src/amd/compiler/aco_insert_waitcnt.cpp @@ -1004,7 +1004,6 @@ emit_waitcnt(wait_ctx& ctx, std::vector>& instructions, wai SOPP_instruction* waitcnt = create_instruction(aco_opcode::s_waitcnt, Format::SOPP, 0, 0); waitcnt->imm = imm.pack(ctx.gfx_level); - waitcnt->block = -1; instructions.emplace_back(waitcnt); } imm = wait_imm(); @@ -1034,7 +1033,6 @@ emit_delay_alu(wait_ctx& ctx, std::vector>& instructions, SOPP_instruction* inst = create_instruction(aco_opcode::s_delay_alu, Format::SOPP, 0, 0); inst->imm = imm; - inst->block = -1; inst->pass_flags = (delay.valu_cycles | (delay.trans_cycles << 16)); instructions.emplace_back(inst); delay = alu_delay_info(); diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index b60aecbf47f..34c88417523 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -9062,7 +9062,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) case nir_intrinsic_sendmsg_amd: { unsigned imm = nir_intrinsic_base(instr); Temp m0_content = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa)); - bld.sopp(aco_opcode::s_sendmsg, bld.m0(m0_content), -1, imm); + bld.sopp(aco_opcode::s_sendmsg, bld.m0(m0_content), imm); break; } case nir_intrinsic_load_gs_wave_id_amd: { @@ -11713,7 +11713,7 @@ pops_await_overlapped_waves(isel_context* ctx) /* GFX11+ - waiting for the export from the overlapped waves. * Await the export_ready event (bit wait_event_imm_dont_wait_export_ready clear). */ - bld.sopp(aco_opcode::s_wait_event, -1, 0); + bld.sopp(aco_opcode::s_wait_event, 0); return; } @@ -11805,7 +11805,7 @@ pops_await_overlapped_waves(isel_context* ctx) bld.reset(ctx->block); /* Sleep before rechecking to let overlapped waves run for some time. */ - bld.sopp(aco_opcode::s_sleep, -1, ctx->program->gfx_level >= GFX10 ? UINT16_MAX : 3); + bld.sopp(aco_opcode::s_sleep, ctx->program->gfx_level >= GFX10 ? UINT16_MAX : 3); end_loop(ctx, &wait_loop_context); bld.reset(ctx->block); @@ -11895,7 +11895,7 @@ select_shader(isel_context& ctx, nir_shader* nir, const bool need_startpgm, cons if (!program->info.vs.has_prolog && (program->stage.has(SWStage::VS) || program->stage.has(SWStage::TES))) { - Builder(ctx.program, ctx.block).sopp(aco_opcode::s_setprio, -1u, 0x3u); + Builder(ctx.program, ctx.block).sopp(aco_opcode::s_setprio, 0x3u); } } @@ -11904,7 +11904,7 @@ select_shader(isel_context& ctx, nir_shader* nir, const bool need_startpgm, cons /* Workaround for Navi1x HW bug to ensure that all NGG waves launch before * s_sendmsg(GS_ALLOC_REQ). */ - Builder(ctx.program, ctx.block).sopp(aco_opcode::s_barrier, -1u, 0u); + Builder(ctx.program, ctx.block).sopp(aco_opcode::s_barrier, 0u); } if (check_merged_wave_info) { @@ -12468,7 +12468,7 @@ load_vb_descs(Builder& bld, PhysReg dest, Operand base, unsigned start, unsigned unsigned num_loads = (count / 4u) + util_bitcount(count & 0x3); if (bld.program->gfx_level >= GFX10 && num_loads > 1) - bld.sopp(aco_opcode::s_clause, -1, num_loads - 1); + bld.sopp(aco_opcode::s_clause, num_loads - 1); for (unsigned i = 0; i < count;) { unsigned size = 1u << util_logbase2(MIN2(count - i, 4)); @@ -12501,7 +12501,7 @@ calc_nontrivial_instance_id(Builder& bld, const struct ac_shader_args* args, wait_imm lgkm_imm; lgkm_imm.lgkm = 0; - bld.sopp(aco_opcode::s_waitcnt, -1, lgkm_imm.pack(bld.program->gfx_level)); + bld.sopp(aco_opcode::s_waitcnt, lgkm_imm.pack(bld.program->gfx_level)); Definition fetch_index_def(tmp_vgpr0, v1); Operand fetch_index(tmp_vgpr0, v1); @@ -12777,7 +12777,7 @@ select_vs_prolog(Program* program, const struct aco_vs_prolog_info* pinfo, ac_sh block->instructions.reserve(16 + pinfo->num_attributes * 4); - bld.sopp(aco_opcode::s_setprio, -1u, 0x3u); + bld.sopp(aco_opcode::s_setprio, 0x3u); uint32_t attrib_mask = BITFIELD_MASK(pinfo->num_attributes); bool has_nontrivial_divisors = pinfo->nontrivial_divisors; @@ -12882,7 +12882,7 @@ select_vs_prolog(Program* program, const struct aco_vs_prolog_info* pinfo, ac_sh bld.vop1(aco_opcode::v_mov_b32, Definition(start_instance_vgpr, v1), start_instance); } - bld.sopp(aco_opcode::s_waitcnt, -1, lgkm_imm.pack(program->gfx_level)); + bld.sopp(aco_opcode::s_waitcnt, lgkm_imm.pack(program->gfx_level)); for (unsigned i = 0; i < num_descs;) { PhysReg dest(attributes_start.reg() + loc * 4u); @@ -12964,7 +12964,7 @@ select_vs_prolog(Program* program, const struct aco_vs_prolog_info* pinfo, ac_sh if (pinfo->alpha_adjust_lo | pinfo->alpha_adjust_hi) { wait_imm vm_imm; vm_imm.vm = 0; - bld.sopp(aco_opcode::s_waitcnt, -1, vm_imm.pack(program->gfx_level)); + bld.sopp(aco_opcode::s_waitcnt, vm_imm.pack(program->gfx_level)); } /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW. @@ -13005,7 +13005,7 @@ select_vs_prolog(Program* program, const struct aco_vs_prolog_info* pinfo, ac_sh if (has_nontrivial_divisors) { bld.smem(aco_opcode::s_load_dwordx2, Definition(prolog_input, s2), get_arg_fixed(args, pinfo->inputs), Operand::c32(0u)); - bld.sopp(aco_opcode::s_waitcnt, -1, lgkm_imm.pack(program->gfx_level)); + bld.sopp(aco_opcode::s_waitcnt, lgkm_imm.pack(program->gfx_level)); continue_pc = Operand(prolog_input, s2); } diff --git a/src/amd/compiler/aco_ir.cpp b/src/amd/compiler/aco_ir.cpp index 4c2361b37e5..866eb2452ae 100644 --- a/src/amd/compiler/aco_ir.cpp +++ b/src/amd/compiler/aco_ir.cpp @@ -1378,8 +1378,8 @@ dealloc_vgprs(Program* program) if (!block.instructions.empty() && block.instructions.back()->opcode == aco_opcode::s_endpgm) { bld.reset(&block.instructions, block.instructions.begin() + (block.instructions.size() - 1)); /* Due to a hazard, an s_nop is needed before "s_sendmsg sendmsg_dealloc_vgprs". */ - bld.sopp(aco_opcode::s_nop, -1, 0); - bld.sopp(aco_opcode::s_sendmsg, -1, sendmsg_dealloc_vgprs); + bld.sopp(aco_opcode::s_nop, 0); + bld.sopp(aco_opcode::s_sendmsg, sendmsg_dealloc_vgprs); } return true; diff --git a/src/amd/compiler/aco_ir.h b/src/amd/compiler/aco_ir.h index d6f83822278..0921c2f6585 100644 --- a/src/amd/compiler/aco_ir.h +++ b/src/amd/compiler/aco_ir.h @@ -1314,10 +1314,12 @@ struct SOPK_instruction : public Instruction { static_assert(sizeof(SOPK_instruction) == sizeof(Instruction) + 4, "Unexpected padding"); struct SOPP_instruction : public Instruction { + /* In case of branch instructions, contains the Block index, + * and otherwise, the 16-bit signed immediate. + */ uint32_t imm; - int block; }; -static_assert(sizeof(SOPP_instruction) == sizeof(Instruction) + 8, "Unexpected padding"); +static_assert(sizeof(SOPP_instruction) == sizeof(Instruction) + 4, "Unexpected padding"); struct SOPC_instruction : public Instruction { uint32_t padding; diff --git a/src/amd/compiler/aco_lower_to_hw_instr.cpp b/src/amd/compiler/aco_lower_to_hw_instr.cpp index d62e0a530f5..18554e9dfc9 100644 --- a/src/amd/compiler/aco_lower_to_hw_instr.cpp +++ b/src/amd/compiler/aco_lower_to_hw_instr.cpp @@ -2154,9 +2154,9 @@ emit_set_mode(Builder& bld, float_mode new_mode, bool set_round, bool set_denorm { if (bld.program->gfx_level >= GFX10) { if (set_round) - bld.sopp(aco_opcode::s_round_mode, -1, new_mode.round); + bld.sopp(aco_opcode::s_round_mode, new_mode.round); if (set_denorm) - bld.sopp(aco_opcode::s_denorm_mode, -1, new_mode.denorm); + bld.sopp(aco_opcode::s_denorm_mode, new_mode.denorm); } else if (set_round || set_denorm) { /* "((size - 1) << 11) | register" (MODE is encoded as register 1) */ bld.sopk(aco_opcode::s_setreg_imm32_b32, Operand::literal32(new_mode.val), (7 << 11) | 1); @@ -2313,7 +2313,7 @@ lower_to_hw_instr(Program* program) instr_idx == pops_done_msg_bounds.instr_after_end_idx()) || (instr->opcode == aco_opcode::s_endpgm && pops_done_msg_bounds.early_exit_needs_done_msg(block_idx, instr_idx))) { - bld.sopp(aco_opcode::s_sendmsg, -1, sendmsg_ordered_ps_done); + bld.sopp(aco_opcode::s_sendmsg, sendmsg_ordered_ps_done); } aco_ptr mov; @@ -2457,11 +2457,10 @@ lower_to_hw_instr(Program* program) pops_exit_wait_imm.vm = 0; if (program->has_smem_buffer_or_global_loads) pops_exit_wait_imm.lgkm = 0; - bld.sopp(aco_opcode::s_waitcnt, -1, - pops_exit_wait_imm.pack(program->gfx_level)); + bld.sopp(aco_opcode::s_waitcnt, pops_exit_wait_imm.pack(program->gfx_level)); } if (discard_sends_pops_done) - bld.sopp(aco_opcode::s_sendmsg, -1, sendmsg_ordered_ps_done); + bld.sopp(aco_opcode::s_sendmsg, sendmsg_ordered_ps_done); unsigned target = V_008DFC_SQ_EXP_NULL; if (program->gfx_level >= GFX11) target = @@ -2470,7 +2469,7 @@ lower_to_hw_instr(Program* program) bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1), 0, target, false, true, true); if (should_dealloc_vgprs) - bld.sopp(aco_opcode::s_sendmsg, -1, sendmsg_dealloc_vgprs); + bld.sopp(aco_opcode::s_sendmsg, sendmsg_dealloc_vgprs); bld.sopp(aco_opcode::s_endpgm); bld.reset(&ctx.instructions); @@ -2728,7 +2727,7 @@ lower_to_hw_instr(Program* program) } case aco_opcode::p_jump_to_epilog: { if (pops_done_msg_bounds.early_exit_needs_done_msg(block_idx, instr_idx)) { - bld.sopp(aco_opcode::s_sendmsg, -1, sendmsg_ordered_ps_done); + bld.sopp(aco_opcode::s_sendmsg, sendmsg_ordered_ps_done); } bld.sop1(aco_opcode::s_setpc_b64, instr->operands[0]); break; @@ -2896,7 +2895,7 @@ lower_to_hw_instr(Program* program) bool is_break_continue = program->blocks[i].kind & (block_kind_break | block_kind_continue); bool discard_early_exit = - program->blocks[inst->sopp().block].kind & block_kind_discard_early_exit; + program->blocks[inst->sopp().imm].kind & block_kind_discard_early_exit; if ((inst->opcode != aco_opcode::s_cbranch_scc0 && inst->opcode != aco_opcode::s_cbranch_scc1) || (!discard_early_exit && !is_break_continue)) @@ -3035,7 +3034,7 @@ lower_to_hw_instr(Program* program) */ if (block_idx == pops_done_msg_bounds.end_block_idx() && pops_done_msg_bounds.instr_after_end_idx() >= block->instructions.size()) { - bld.sopp(aco_opcode::s_sendmsg, -1, sendmsg_ordered_ps_done); + bld.sopp(aco_opcode::s_sendmsg, sendmsg_ordered_ps_done); } block->instructions = std::move(ctx.instructions); diff --git a/src/amd/compiler/aco_opcodes.py b/src/amd/compiler/aco_opcodes.py index e15c046b31e..0e736513f0c 100644 --- a/src/amd/compiler/aco_opcodes.py +++ b/src/amd/compiler/aco_opcodes.py @@ -106,8 +106,7 @@ class Format(IntEnum): if self == Format.SOPK: return [('uint16_t', 'imm', None)] elif self == Format.SOPP: - return [('uint32_t', 'block', '-1'), - ('uint32_t', 'imm', '0')] + return [('uint32_t', 'imm', '0')] elif self == Format.SMEM: return [('memory_sync_info', 'sync', 'memory_sync_info()'), ('bool', 'glc', 'false'), diff --git a/src/amd/compiler/aco_print_ir.cpp b/src/amd/compiler/aco_print_ir.cpp index 58de0323838..2fe73672ee5 100644 --- a/src/amd/compiler/aco_print_ir.cpp +++ b/src/amd/compiler/aco_print_ir.cpp @@ -399,13 +399,13 @@ print_instr_format_specific(enum amd_gfx_level gfx_level, const Instruction* ins break; } default: { - if (imm) + if (instr_info.classes[(int)instr->opcode] == instr_class::branch) + fprintf(output, " block:BB%d", instr->sopp().imm); + else if (imm) fprintf(output, " imm:%u", imm); break; } } - if (instr_info.classes[(int)instr->opcode] == instr_class::branch) - fprintf(output, " block:BB%d", instr->sopp().block); break; } case Format::SOP1: { diff --git a/src/amd/compiler/tests/test_assembler.cpp b/src/amd/compiler/tests/test_assembler.cpp index 0b2fd97b41a..f47d354701c 100644 --- a/src/amd/compiler/tests/test_assembler.cpp +++ b/src/amd/compiler/tests/test_assembler.cpp @@ -79,7 +79,7 @@ BEGIN_TEST(assembler.long_jump.unconditional_forwards) //! s_nop 0 ; bf800000 //!(then repeated 32767 times) for (unsigned i = 0; i < INT16_MAX + 1; i++) - bld.sopp(aco_opcode::s_nop, -1, 0); + bld.sopp(aco_opcode::s_nop, 0); //! BB2: //! s_endpgm ; bf810000 @@ -110,7 +110,7 @@ BEGIN_TEST(assembler.long_jump.conditional_forwards) //! s_nop 0 ; bf800000 //!(then repeated 32767 times) for (unsigned i = 0; i < INT16_MAX + 1; i++) - bld.sopp(aco_opcode::s_nop, -1, 0); + bld.sopp(aco_opcode::s_nop, 0); //! BB2: //! s_endpgm ; bf810000 @@ -131,7 +131,7 @@ BEGIN_TEST(assembler.long_jump.unconditional_backwards) //! s_nop 0 ; bf800000 //!(then repeated 32767 times) for (unsigned i = 0; i < INT16_MAX + 1; i++) - bld.sopp(aco_opcode::s_nop, -1, 0); + bld.sopp(aco_opcode::s_nop, 0); //! s_getpc_b64 s[0:1] ; be801f00 //! s_addc_u32 s0, s0, 0xfffdfffc ; 8200ff00 fffdfffc @@ -158,7 +158,7 @@ BEGIN_TEST(assembler.long_jump.conditional_backwards) //! s_nop 0 ; bf800000 //!(then repeated 32767 times) for (unsigned i = 0; i < INT16_MAX + 1; i++) - bld.sopp(aco_opcode::s_nop, -1, 0); + bld.sopp(aco_opcode::s_nop, 0); //! s_cbranch_execz BB1 ; bf880006 //! s_getpc_b64 s[0:1] ; be801f00 @@ -213,7 +213,7 @@ BEGIN_TEST(assembler.long_jump.constaddr) bld.reset(program->create_and_insert_block()); for (unsigned i = 0; i < INT16_MAX + 1; i++) - bld.sopp(aco_opcode::s_nop, -1, 0); + bld.sopp(aco_opcode::s_nop, 0); bld.reset(program->create_and_insert_block()); @@ -249,7 +249,7 @@ BEGIN_TEST(assembler.long_jump.discard_early_exit) //!(then repeated 32766 times) //! s_endpgm ; bf810000 for (unsigned i = 0; i < INT16_MAX; i++) - bld.sopp(aco_opcode::s_nop, -1, 1); + bld.sopp(aco_opcode::s_nop, 1); //! BB2: //! s_endpgm ; bf810000 diff --git a/src/amd/compiler/tests/test_insert_nops.cpp b/src/amd/compiler/tests/test_insert_nops.cpp index 89c66924e48..8ac8766bbb8 100644 --- a/src/amd/compiler/tests/test_insert_nops.cpp +++ b/src/amd/compiler/tests/test_insert_nops.cpp @@ -259,7 +259,7 @@ BEGIN_TEST(insert_nops.vmem_to_scalar_write) //! s1: %0:s[0] = s_mov_b32 0 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(8)); create_mubuf(0); - bld.sopp(aco_opcode::s_waitcnt, -1, 0x3f70); + bld.sopp(aco_opcode::s_waitcnt, 0x3f70); bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(0), s1), Operand::zero()); //! p_unit_test 9 @@ -278,7 +278,7 @@ BEGIN_TEST(insert_nops.vmem_to_scalar_write) bld.pseudo(aco_opcode::p_unit_test, Operand::c32(10)); bld.ds(aco_opcode::ds_read_b32, Definition(PhysReg(256), v1), Operand(PhysReg(256), v1), Operand(m0, s1)); - bld.sopp(aco_opcode::s_waitcnt, -1, 0xc07f); + bld.sopp(aco_opcode::s_waitcnt, 0xc07f); bld.sop1(aco_opcode::s_mov_b32, Definition(m0, s1), Operand::zero()); /* VMEM/LDS with the wrong waitcnt in-between */ @@ -299,7 +299,7 @@ BEGIN_TEST(insert_nops.vmem_to_scalar_write) //! s1: %0:s[0] = s_mov_b32 0 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(12)); create_mubuf_store(); - bld.sopp(aco_opcode::s_waitcnt, -1, 0xc07f); + bld.sopp(aco_opcode::s_waitcnt, 0xc07f); bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(0), s1), Operand::zero()); //! p_unit_test 13 @@ -310,7 +310,7 @@ BEGIN_TEST(insert_nops.vmem_to_scalar_write) bld.pseudo(aco_opcode::p_unit_test, Operand::c32(13)); bld.ds(aco_opcode::ds_read_b32, Definition(PhysReg(256), v1), Operand(PhysReg(256), v1), Operand(m0, s1)); - bld.sopp(aco_opcode::s_waitcnt, -1, 0x3f70); + bld.sopp(aco_opcode::s_waitcnt, 0x3f70); bld.sop1(aco_opcode::s_mov_b32, Definition(m0, s1), Operand::zero()); finish_insert_nops_test(); @@ -436,7 +436,7 @@ BEGIN_TEST(insert_nops.lds_direct_valu) bld.pseudo(aco_opcode::p_unit_test, Operand::c32(11)); bld.vop1(aco_opcode::v_mov_b32, Definition(PhysReg(256), v1), Operand::zero()); bld.vop1(aco_opcode::v_nop); - bld.sopp(aco_opcode::s_waitcnt_depctr, -1, 0x0fff); + bld.sopp(aco_opcode::s_waitcnt_depctr, 0x0fff); bld.ldsdir(aco_opcode::lds_direct_load, Definition(PhysReg(256), v1), Operand(m0, s1)); finish_insert_nops_test(); @@ -525,7 +525,7 @@ BEGIN_TEST(insert_nops.lds_direct_vmem) //! v1: %0:v[0] = lds_direct_load %0:m0 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(8)); create_mubuf(0, PhysReg(257)); - bld.sopp(aco_opcode::s_waitcnt, -1, 0x3ff); + bld.sopp(aco_opcode::s_waitcnt, 0x3ff); bld.ldsdir(aco_opcode::lds_direct_load, Definition(PhysReg(256), v1), Operand(m0, s1)); //! p_unit_test 9 @@ -543,7 +543,7 @@ BEGIN_TEST(insert_nops.lds_direct_vmem) //! v1: %0:v[0] = lds_direct_load %0:m0 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(10)); bld.ds(aco_opcode::ds_read_b32, Definition(PhysReg(257), v1), Operand(PhysReg(256), v1)); - bld.sopp(aco_opcode::s_waitcnt, -1, 0xfc0f); + bld.sopp(aco_opcode::s_waitcnt, 0xfc0f); bld.ldsdir(aco_opcode::lds_direct_load, Definition(PhysReg(256), v1), Operand(m0, s1)); /* VMEM/LDS with the wrong waitcnt in-between */ @@ -564,7 +564,7 @@ BEGIN_TEST(insert_nops.lds_direct_vmem) //! v1: %0:v[0] = lds_direct_load %0:m0 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(12)); create_mubuf_store(); - bld.sopp(aco_opcode::s_waitcnt, -1, 0xfc0f); + bld.sopp(aco_opcode::s_waitcnt, 0xfc0f); bld.ldsdir(aco_opcode::lds_direct_load, Definition(PhysReg(256), v1), Operand(m0, s1)); //! p_unit_test 13 @@ -574,7 +574,7 @@ BEGIN_TEST(insert_nops.lds_direct_vmem) //! v1: %0:v[0] = lds_direct_load %0:m0 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(13)); bld.ds(aco_opcode::ds_read_b32, Definition(PhysReg(257), v1), Operand(PhysReg(256), v1)); - bld.sopp(aco_opcode::s_waitcnt, -1, 0x3ff); + bld.sopp(aco_opcode::s_waitcnt, 0x3ff); bld.ldsdir(aco_opcode::lds_direct_load, Definition(PhysReg(256), v1), Operand(m0, s1)); //! p_unit_test 14 @@ -668,7 +668,7 @@ BEGIN_TEST(insert_nops.valu_trans_use) bld.pseudo(aco_opcode::p_unit_test, Operand::c32(6)); bld.vop1(aco_opcode::v_rcp_f32, Definition(PhysReg(256), v1), Operand(PhysReg(257), v1)); for (unsigned i = 0; i < 8; i++) - bld.sopp(aco_opcode::s_nop, -1, 0); + bld.sopp(aco_opcode::s_nop, 0); bld.vop1(aco_opcode::v_mov_b32, Definition(PhysReg(257), v1), Operand(PhysReg(256), v1)); finish_insert_nops_test(); @@ -991,7 +991,7 @@ BEGIN_TEST(insert_nops.valu_mask_write) bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(PhysReg(256), v1), Operand::zero(), Operand::zero(), Operand(PhysReg(0), s2)); bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(1), s1), Operand::zero()); - bld.sopp(aco_opcode::s_waitcnt_depctr, -1, 0xfffe); + bld.sopp(aco_opcode::s_waitcnt_depctr, 0xfffe); bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(2), s1), Operand(PhysReg(1), s1)); /* Instruction which is both involved in the hazard and is a mitigation. */ @@ -1028,7 +1028,7 @@ BEGIN_TEST(insert_nops.setpc_gfx6) //! s_setpc_b64 0 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(1)); bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(0), s1), Operand::zero()); - bld.sopp(aco_opcode::s_nop, -1, 2); + bld.sopp(aco_opcode::s_nop, 2); bld.sop1(aco_opcode::s_setpc_b64, Operand::zero(8)); finish_insert_nops_test();