diff --git a/src/freedreno/ir3/instr-a3xx.h b/src/freedreno/ir3/instr-a3xx.h
index 787a539eaff..92b78372b6f 100644
--- a/src/freedreno/ir3/instr-a3xx.h
+++ b/src/freedreno/ir3/instr-a3xx.h
@@ -202,6 +202,10 @@ typedef enum {
    OPC_DP4ACC          = _OPC(3, 22),
    OPC_WMM             = _OPC(3, 23),
    OPC_WMM_ACCU        = _OPC(3, 24),
+   OPC_MAD_F16_MUL2    = _OPC(3, 25),
+   OPC_MAD_F32_MUL2    = _OPC(3, 26),
+   OPC_MAD_F16_DIV2    = _OPC(3, 27),
+   OPC_MAD_F32_DIV2    = _OPC(3, 28),
 
    /* category 4: */
    OPC_RCP             = _OPC(4, 0),
diff --git a/src/freedreno/ir3/ir3_parser.y b/src/freedreno/ir3/ir3_parser.y
index a18f0e57da2..0f77c455419 100644
--- a/src/freedreno/ir3/ir3_parser.y
+++ b/src/freedreno/ir3/ir3_parser.y
@@ -830,7 +830,11 @@ cat3_dp_signedness:'.' T_MIXED   { instr->cat3.signedness = IR3_SRC_MIXED; }
 cat3_dp_pack:      '.' T_LOW     { instr->cat3.packed = IR3_SRC_PACKED_LOW; }
 |                  '.' T_HIGH    { instr->cat3.packed = IR3_SRC_PACKED_HIGH; }
 
-cat3_opc:          T_OP_MAD_F16   { new_instr(OPC_MAD_F16); }
+cat3_opc:          T_OP_MAD_F16 T_MUL2 { new_instr(OPC_MAD_F16_MUL2); }
+|                  T_OP_MAD_F32 T_MUL2 { new_instr(OPC_MAD_F32_MUL2); }
+|                  T_OP_MAD_F16 T_DIV2 { new_instr(OPC_MAD_F16_DIV2); }
+|                  T_OP_MAD_F32 T_DIV2 { new_instr(OPC_MAD_F32_DIV2); }
+|                  T_OP_MAD_F16   { new_instr(OPC_MAD_F16); }
 |                  T_OP_MAD_F32   { new_instr(OPC_MAD_F32); }
 |                  T_OP_SEL_F16   { new_instr(OPC_SEL_F16); }
 |                  T_OP_SEL_F32   { new_instr(OPC_SEL_F32); }
diff --git a/src/freedreno/ir3/tests/disasm.c b/src/freedreno/ir3/tests/disasm.c
index 53990a73dd3..df3ba0f5092 100644
--- a/src/freedreno/ir3/tests/disasm.c
+++ b/src/freedreno/ir3/tests/disasm.c
@@ -157,6 +157,7 @@ static const struct test {
 
    INSTR_7XX(61808000_04020400, "madsh.m16 r0.x, (last)r0.x, r0.y, (last)r0.z"),
    INSTR_7XX(64838806_04088406, "(nop3) sel.b32 r1.z, (last)r1.z, r1.w, (last)r2.x"),
+   INSTR_7XX(6286880e_040ee002, "(nop3) mad.f32.mul2 r3.z, (neg)r0.z, r3.y, (last)r3.z"),
    INSTR_8XX(6206000a_040a0610, "mad.u24 r2.z, 16, r3.x, (last)r2.z"),
    INSTR_8XX(62000800_06030402, "(nop1) mad.u24 r0.x, (last)r0.z, r0.x, 3"),
    INSTR_8XX(63820009_07024409, "mad.f32 r2.y, (neg)(last)r2.y, r1.x, (1.0)"),
diff --git a/src/freedreno/isa/ir3-cat3.xml b/src/freedreno/isa/ir3-cat3.xml
index abb8984e2fb..fc350279f16 100644
--- a/src/freedreno/isa/ir3-cat3.xml
+++ b/src/freedreno/isa/ir3-cat3.xml
@@ -170,8 +170,6 @@ SOFTWARE.
 	</field>
 	<field name="SRC1_NEG" pos="14" type="bool" display="(neg)"/>
 
-	<pattern pos="13">0</pattern>
-
 	<field name="SRC3" low="16" high="28" type="#cat3-src">
 		<param name="HALF"/>
 		<param name="IMMED_ENCODING"/>
@@ -216,7 +214,7 @@ SOFTWARE.
 	</field>
 	<field name="SRC1_NEG" pos="14" type="bool" display="(neg)"/>
 
-	<pattern pos="13">1</pattern>
+	<pattern pos="13">1</pattern>  <!-- AL OP -->
 
 	<field name="SRC3" low="16" high="28" type="#cat3-src">
 		<param name="HALF"/>
@@ -239,85 +237,129 @@ SOFTWARE.
 </bitset>
 
 <bitset name="mad.u16" extends="#instruction-cat3">
+	<pattern pos="13">0</pattern>  <!-- AL OP -->
 	<pattern low="55" high="58">0000</pattern>   <!-- OPC -->
 	<derived name="FULL" expr="#false" type="bool"/>
 </bitset>
 
 <bitset name="madsh.u16" extends="#instruction-cat3">
+	<pattern pos="13">0</pattern>  <!-- AL OP -->
 	<pattern low="55" high="58">0001</pattern>   <!-- OPC -->
 	<derived name="FULL" expr="#true" type="bool"/>
 </bitset>
 
 <bitset name="mad.s16" extends="#instruction-cat3">
+	<pattern pos="13">0</pattern>  <!-- AL OP -->
 	<pattern low="55" high="58">0010</pattern>   <!-- OPC -->
 	<derived name="FULL" expr="#false" type="bool"/>
 </bitset>
 
 <bitset name="madsh.m16" extends="#instruction-cat3">
+	<pattern pos="13">0</pattern>  <!-- AL OP -->
 	<pattern low="55" high="58">0011</pattern>   <!-- OPC -->
 	<derived name="FULL" expr="#true" type="bool"/>
 </bitset>
 
 <bitset name="mad.u24" extends="#instruction-cat3">
+	<pattern pos="13">0</pattern>  <!-- AL OP -->
 	<pattern low="55" high="58">0100</pattern>   <!-- OPC -->
 	<derived name="FULL" expr="#true" type="bool"/>
 </bitset>
 
 <bitset name="mad.s24" extends="#instruction-cat3">
+	<pattern pos="13">0</pattern>  <!-- AL OP -->
 	<pattern low="55" high="58">0101</pattern>   <!-- OPC -->
 	<derived name="FULL" expr="#true" type="bool"/>
 </bitset>
 
 <bitset name="mad.f16" extends="#instruction-cat3">
+	<pattern pos="13">0</pattern>  <!-- AL OP -->
 	<pattern low="55" high="58">0110</pattern>   <!-- OPC -->
 	<derived name="FULL" expr="#false" type="bool"/>
 </bitset>
 
 <bitset name="mad.f32" extends="#instruction-cat3">
+	<pattern pos="13">0</pattern>  <!-- AL OP -->
 	<pattern low="55" high="58">0111</pattern>   <!-- OPC -->
 	<derived name="FULL" expr="#true" type="bool"/>
 </bitset>
 
 <bitset name="sel.b16" extends="#instruction-cat3">
+	<pattern pos="13">0</pattern>  <!-- AL OP -->
 	<pattern low="55" high="58">1000</pattern>   <!-- OPC -->
 	<derived name="FULL" expr="#false" type="bool"/>
 </bitset>
 
 <bitset name="sel.b32" extends="#instruction-cat3">
+	<pattern pos="13">0</pattern>  <!-- AL OP -->
 	<pattern low="55" high="58">1001</pattern>   <!-- OPC -->
 	<derived name="FULL" expr="#true" type="bool"/>
 </bitset>
 
 <bitset name="sel.s16" extends="#instruction-cat3">
+	<pattern pos="13">0</pattern>  <!-- AL OP -->
 	<pattern low="55" high="58">1010</pattern>   <!-- OPC -->
 	<derived name="FULL" expr="#false" type="bool"/>
 </bitset>
 
 <bitset name="sel.s32" extends="#instruction-cat3">
+	<pattern pos="13">0</pattern>  <!-- AL OP -->
 	<pattern low="55" high="58">1011</pattern>   <!-- OPC -->
 	<derived name="FULL" expr="#true" type="bool"/>
 </bitset>
 
 <bitset name="sel.f16" extends="#instruction-cat3">
+	<pattern pos="13">0</pattern>  <!-- AL OP -->
 	<pattern low="55" high="58">1100</pattern>   <!-- OPC -->
 	<derived name="FULL" expr="#false" type="bool"/>
 </bitset>
 
 <bitset name="sel.f32" extends="#instruction-cat3">
+	<pattern pos="13">0</pattern>  <!-- AL OP -->
 	<pattern low="55" high="58">1101</pattern>   <!-- OPC -->
 	<derived name="FULL" expr="#true" type="bool"/>
 </bitset>
 
 <bitset name="sad.s16" extends="#instruction-cat3">
+	<pattern pos="13">0</pattern>  <!-- AL OP -->
 	<pattern low="55" high="58">1110</pattern>   <!-- OPC -->
 	<derived name="FULL" expr="#false" type="bool"/>
 </bitset>
 
 <bitset name="sad.s32" extends="#instruction-cat3">
+	<pattern pos="13">0</pattern>  <!-- AL OP -->
 	<pattern low="55" high="58">1111</pattern>   <!-- OPC -->
 	<derived name="FULL" expr="#true" type="bool"/>
 </bitset>
 
+<bitset name="mad.f16.mul2" extends="#instruction-cat3">
+	<gen min="700"/>
+	<pattern pos="13">1</pattern>  <!-- AL OP -->
+	<pattern low="55" high="58">0100</pattern>   <!-- OPC -->
+	<derived name="FULL" expr="#false" type="bool"/>
+</bitset>
+
+<bitset name="mad.f32.mul2" extends="#instruction-cat3">
+	<gen min="700"/>
+	<pattern pos="13">1</pattern>  <!-- AL OP -->
+	<pattern low="55" high="58">0101</pattern>   <!-- OPC -->
+	<derived name="FULL" expr="#true" type="bool"/>
+</bitset>
+
+<bitset name="mad.f16.div2" extends="#instruction-cat3">
+	<gen min="700"/>
+	<pattern pos="13">1</pattern>  <!-- AL OP -->
+	<pattern low="55" high="58">0110</pattern>   <!-- OPC -->
+	<derived name="FULL" expr="#false" type="bool"/>
+</bitset>
+
+<bitset name="mad.f32.div2" extends="#instruction-cat3">
+	<gen min="700"/>
+	<pattern pos="13">1</pattern>  <!-- AL OP -->
+	<pattern low="55" high="58">0111</pattern>   <!-- OPC -->
+	<derived name="FULL" expr="#true" type="bool"/>
+</bitset>
+
 <bitset name="shrm" extends="#instruction-cat3-alt">
 	<doc>
 		(src2 &gt;&gt; src1) &amp; src3