From 5c68b351feaa63b307881d756dd9e1acf1b500f4 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Thu, 11 Sep 2025 15:59:05 -0700 Subject: [PATCH] intel/brw: Fix regression in brw_allocate_registers() compiling large shaders with throughput==0. The following Vulkan CTS tests that emit massive shaders were regressing after "intel/brw/xe3+: Select scheduler heuristic with best trade-off between register pressure and latency.": dEQP-VK.graphicsfuzz.cov-nested-loops-set-struct-data-verify-in-function dEQP-VK.graphicsfuzz.cov-dfdx-dfdy-after-nested-loops The reason is that they have so many nested loops that they cause the performance analysis utilization estimates to overflow the 32-bit floating-point variables used to calculate them, which causes our throughput estimate to underflow and equal zero for those shaders, which breaks the logic introduced in brw_allocate_registers() to select the scheduling variant with highest throughput, since none of the scheduling modes tried has better throughput than the initial value equal to zero of "best_perf". Instead use -INFINITY as initial value for "best_perf" so we always select a scheduling mode. This should have been caught by CI but oddly the tests above are showing up as "not run" on my last baseline runs, so this wasn't flagged as a regression for me. v2: Use -INFINITY instead of previous approach that used NaN (Ian). Fixes: 531a34c7ddf216749 ("intel/brw/xe3+: Select scheduler heuristic with best trade-off between register pressure and latency.") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13884 Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13885 Reviewed-by: Lionel Landwerlin (v1) Reviewed-by: Ian Romanick Part-of: --- src/intel/compiler/brw_shader.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index f0f26199aa1..2e7e6d7a977 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -1117,7 +1117,7 @@ brw_allocate_registers(brw_shader &s, bool allow_spilling) }; uint32_t best_register_pressure = UINT32_MAX; - float best_perf = 0; + float best_perf = -INFINITY; unsigned best_press_idx = 0; unsigned best_perf_idx = 0;