diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c
index f72a556a1b2..fe44a6b09f1 100644
--- a/src/intel/compiler/brw_compiler.c
+++ b/src/intel/compiler/brw_compiler.c
@@ -94,7 +94,7 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
 
    brw_init_isa_info(&compiler->isa, devinfo);
 
-   brw_fs_alloc_reg_sets(compiler);
+   brw_alloc_reg_sets(compiler);
 
    compiler->precise_trig = debug_get_bool_option("INTEL_PRECISE_TRIG", false);
 
diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h
index c4f137c5f95..3908730b9b6 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -1486,11 +1486,11 @@ brw_stage_has_packed_dispatch(ASSERTED const struct intel_device_info *devinfo,
 {
    /* The code below makes assumptions about the hardware's thread dispatch
     * behavior that could be proven wrong in future generations -- Make sure
-    * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
+    * to do a full test run with brw_test_dispatch_packing() hooked up to
     * the NIR front-end before changing this assertion. It can be temporarily
     * enabled by setting the macro below to true.
     */
-   #define ENABLE_FS_TEST_DISPATCH_PACKING false
+   #define ENABLE_TEST_DISPATCH_PACKING false
    assert(devinfo->ver <= 30);
 
    switch (stage) {
diff --git a/src/intel/compiler/brw_from_nir.cpp b/src/intel/compiler/brw_from_nir.cpp
index 215c382cb05..e2498339546 100644
--- a/src/intel/compiler/brw_from_nir.cpp
+++ b/src/intel/compiler/brw_from_nir.cpp
@@ -7789,7 +7789,7 @@ emit_shader_float_controls_execution_mode(nir_to_brw_state &ntb)
  * executed with an unexpected dispatch mask.
  */
 static UNUSED void
-brw_fs_test_dispatch_packing(const brw_builder &bld)
+brw_test_dispatch_packing(const brw_builder &bld)
 {
    const brw_shader *shader = bld.shader;
    const gl_shader_stage stage = shader->stage;
@@ -7830,8 +7830,8 @@ brw_from_nir(brw_shader *s)
    if (INTEL_DEBUG(DEBUG_ANNOTATION))
       ntb.annotate = true;
 
-   if (ENABLE_FS_TEST_DISPATCH_PACKING)
-      brw_fs_test_dispatch_packing(ntb.bld);
+   if (ENABLE_TEST_DISPATCH_PACKING)
+      brw_test_dispatch_packing(ntb.bld);
 
    for (unsigned i = 0; i < s->nir->printf_info_count; i++) {
       brw_stage_prog_data_add_printf(s->prog_data,
diff --git a/src/intel/compiler/brw_inst.cpp b/src/intel/compiler/brw_inst.cpp
index 2755a0e28db..7b86f05d464 100644
--- a/src/intel/compiler/brw_inst.cpp
+++ b/src/intel/compiler/brw_inst.cpp
@@ -643,13 +643,13 @@ brw_inst::flags_read(const intel_device_info *devinfo) const
        * f0.0 and f1.0 on Gfx7+.
        */
       const unsigned shift = 4;
-      return brw_fs_flag_mask(this, 1) << shift | brw_fs_flag_mask(this, 1);
+      return brw_flag_mask(this, 1) << shift | brw_flag_mask(this, 1);
    } else if (predicate) {
-      return brw_fs_flag_mask(this, predicate_width(devinfo, predicate));
+      return brw_flag_mask(this, predicate_width(devinfo, predicate));
    } else {
       unsigned mask = 0;
       for (int i = 0; i < sources; i++) {
-         mask |= brw_fs_flag_mask(src[i], size_read(devinfo, i));
+         mask |= brw_flag_mask(src[i], size_read(devinfo, i));
       }
       return mask;
    }
@@ -662,15 +662,15 @@ brw_inst::flags_written(const intel_device_info *devinfo) const
                            opcode != BRW_OPCODE_CSEL &&
                            opcode != BRW_OPCODE_IF &&
                            opcode != BRW_OPCODE_WHILE)) {
-      return brw_fs_flag_mask(this, 1);
+      return brw_flag_mask(this, 1);
    } else if (opcode == FS_OPCODE_LOAD_LIVE_CHANNELS ||
               opcode == SHADER_OPCODE_BALLOT ||
               opcode == SHADER_OPCODE_VOTE_ANY ||
               opcode == SHADER_OPCODE_VOTE_ALL ||
               opcode == SHADER_OPCODE_VOTE_EQUAL) {
-      return brw_fs_flag_mask(this, 32);
+      return brw_flag_mask(this, 32);
    } else {
-      return brw_fs_flag_mask(dst, size_written);
+      return brw_flag_mask(dst, size_written);
    }
 }
 
diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h
index 97d76d5efee..63c175e824d 100644
--- a/src/intel/compiler/brw_inst.h
+++ b/src/intel/compiler/brw_inst.h
@@ -382,7 +382,7 @@ bool has_bank_conflict(const struct brw_isa_info *isa, const brw_inst *inst);
  * subregister number of the instruction.
  */
 static inline unsigned
-brw_fs_flag_mask(const brw_inst *inst, unsigned width)
+brw_flag_mask(const brw_inst *inst, unsigned width)
 {
    assert(util_is_power_of_two_nonzero(width));
    const unsigned start = (inst->flag_subreg * 16 + inst->group) &
@@ -392,18 +392,18 @@ brw_fs_flag_mask(const brw_inst *inst, unsigned width)
 }
 
 static inline unsigned
-brw_fs_bit_mask(unsigned n)
+brw_bit_mask(unsigned n)
 {
-   return (n >= CHAR_BIT * sizeof(brw_fs_bit_mask(n)) ? ~0u : (1u << n) - 1);
+   return (n >= CHAR_BIT * sizeof(brw_bit_mask(n)) ? ~0u : (1u << n) - 1);
 }
 
 static inline unsigned
-brw_fs_flag_mask(const brw_reg &r, unsigned sz)
+brw_flag_mask(const brw_reg &r, unsigned sz)
 {
    if (r.file == ARF) {
       const unsigned start = (r.nr - BRW_ARF_FLAG) * 4 + r.subnr;
       const unsigned end = start + sz;
-      return brw_fs_bit_mask(end) & ~brw_fs_bit_mask(start);
+      return brw_bit_mask(end) & ~brw_bit_mask(start);
    } else {
       return 0;
    }
diff --git a/src/intel/compiler/brw_lower_simd_width.cpp b/src/intel/compiler/brw_lower_simd_width.cpp
index ed0df236b5b..6c90ba81ecc 100644
--- a/src/intel/compiler/brw_lower_simd_width.cpp
+++ b/src/intel/compiler/brw_lower_simd_width.cpp
@@ -481,7 +481,7 @@ needs_src_copy(const brw_builder &lbld, const brw_inst *inst, unsigned i)
              (inst->components_read(i) == 1 &&
               lbld.dispatch_width() <= inst->exec_size)) ||
            (inst->flags_written(lbld.shader->devinfo) &
-            brw_fs_flag_mask(inst->src[i], brw_type_size_bytes(inst->src[i].type))));
+            brw_flag_mask(inst->src[i], brw_type_size_bytes(inst->src[i].type))));
 }
 
 /**
diff --git a/src/intel/compiler/brw_private.h b/src/intel/compiler/brw_private.h
index 3bc9030bb4d..89a857c9b72 100644
--- a/src/intel/compiler/brw_private.h
+++ b/src/intel/compiler/brw_private.h
@@ -30,8 +30,8 @@
 extern "C" {
 #endif
 
-/* brw_fs_reg_allocate.cpp */
-void brw_fs_alloc_reg_sets(struct brw_compiler *compiler);
+/* brw_reg_allocate.cpp */
+void brw_alloc_reg_sets(struct brw_compiler *compiler);
 
 /* brw_disasm.c */
 extern const char *const conditional_modifier[16];
diff --git a/src/intel/compiler/brw_reg_allocate.cpp b/src/intel/compiler/brw_reg_allocate.cpp
index 330383c1e82..07b61f1481f 100644
--- a/src/intel/compiler/brw_reg_allocate.cpp
+++ b/src/intel/compiler/brw_reg_allocate.cpp
@@ -77,7 +77,7 @@ brw_assign_regs_trivial(brw_shader &s)
 }
 
 extern "C" void
-brw_fs_alloc_reg_sets(struct brw_compiler *compiler)
+brw_alloc_reg_sets(struct brw_compiler *compiler)
 {
    const struct intel_device_info *devinfo = compiler->devinfo;
    int base_reg_count = (devinfo->ver >= 30 ? XE3_MAX_GRF / reg_unit(devinfo) :
diff --git a/src/intel/compiler/brw_workaround.cpp b/src/intel/compiler/brw_workaround.cpp
index 46a03a4cd05..f55b30be8dc 100644
--- a/src/intel/compiler/brw_workaround.cpp
+++ b/src/intel/compiler/brw_workaround.cpp
@@ -236,7 +236,7 @@ brw_workaround_nomask_control_flow(brw_shader &s)
                 * and restore the flag register if it's live.
                 */
                const bool save_flag = flag_liveout &
-                                      brw_fs_flag_mask(flag, s.dispatch_width / 8);
+                                      brw_flag_mask(flag, s.dispatch_width / 8);
                const brw_reg tmp = ubld.group(8, 0).vgrf(flag.type);
 
                if (save_flag) {