From 5bf6602d2395dc6095b5d1cf9e22298b4e4770e4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tapani=20P=C3=A4lli?= Date: Thu, 22 Aug 2024 15:01:02 +0300 Subject: [PATCH] anv: check if RT writes are happening for HasWriteableRT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes: eebb6cd236e ("anv: stop using 3DSTATE_WM::ForceThreadDispatchEnable") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11749 Signed-off-by: Tapani Pälli Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/vulkan/genX_gfx_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/genX_gfx_state.c b/src/intel/vulkan/genX_gfx_state.c index 84d03c42305..4045d7f42cc 100644 --- a/src/intel/vulkan/genX_gfx_state.c +++ b/src/intel/vulkan/genX_gfx_state.c @@ -1073,7 +1073,7 @@ genX(cmd_buffer_flush_gfx_runtime_state)(struct anv_cmd_buffer *cmd_buffer) const uint8_t color_writes = dyn->cb.color_write_enables; bool has_writeable_rt = anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT) && - (color_writes & ((1u << gfx->color_att_count) - 1)) != 0; + !anv_cmd_buffer_all_color_write_masked(cmd_buffer); SET(BLEND_STATE, blend.AlphaToCoverageEnable, dyn->ms.alpha_to_coverage_enable);