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aco: implement nir_op_vec5

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Since sparse fetch/load uses vec5 destinations, it may be possible that we
encounter nir_op_vec5.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>
This commit is contained in:
Rhys Perry
2020-11-23 13:15:20 +00:00
committed by Marge Bot
parent 962c917cea
commit 5a4f6313b1
1 changed files with 2 additions and 1 deletions
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src/amd/compiler/aco_instruction_selection.cpp
+2 -1
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@@ -1197,7 +1197,8 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
switch(instr->op) {
case nir_op_vec2:
case nir_op_vec3:
case nir_op_vec4: {
case nir_op_vec4:
case nir_op_vec5: {
std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
unsigned num = instr->dest.dest.ssa.num_components;
for (unsigned i = 0; i < num; ++i)