From 59f53b07c487dead0884b78f15468eefd52a2dc5 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Tue, 19 Oct 2021 15:18:09 -0700 Subject: [PATCH] i965: Set MOCS for push constant buffers on Haswell and Gfx9+ We set MOCS on Ivybridge/Baytrail, but not Haswell, and not Skylake and later. We shoud set it everywhere. While we're at it, we also set it for null constant buffers, so that we aren't programming a 0 MOCS, to allow us to add some safeguards against that. Reviewed-by: Jason Ekstrand Part-of: --- src/mesa/drivers/dri/i965/genX_state_upload.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index cc62641ea52..cb205c61040 100644 --- a/src/mesa/drivers/dri/i965/genX_state_upload.c +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c @@ -3097,6 +3097,12 @@ genX(upload_push_constant_packets)(struct brw_context *brw) brw_batch_emit(brw, GENX(3DSTATE_CONSTANT_VS), pkt) { pkt._3DCommandSubOpcode = push_constant_opcodes[stage]; +#if GFX_VER >= 9 + pkt.MOCS = mocs; +#elif GFX_VER < 8 + /* MOCS is MBZ on Gfx8 so we skip it there */ + pkt.ConstantBody.MOCS = mocs; +#endif if (stage_state->prog_data) { #if GFX_VERx10 >= 75 /* The Skylake PRM contains the following restriction: @@ -3157,8 +3163,7 @@ genX(upload_push_constant_packets)(struct brw_context *brw) } #else pkt.ConstantBody.ReadLength[0] = stage_state->push_const_size; - pkt.ConstantBody.Buffer[0].offset = - stage_state->push_const_offset | mocs; + pkt.ConstantBody.Buffer[0].offset = stage_state->push_const_offset; #endif } }