broadcom/compiler: always enable per-quad on spill operations

This ensures that any channels used for helper invocations are
also spilled/filled correctly.

Alternatively, we could recursively track all temps that get
involved in computing values that are then used in explicit
(dfdx,dfdy) or implicit (texture coordinates for mipmap or
anisotropic filtering, etc) derivatives, and only enable
per-quad on these (or disable spilling of any of these
values).

Fixes:
dEQP-VK.graphicsfuzz.cov-dfdx-dfdy-after-nested-loops

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15705>

src/broadcom/ci/broadcom-rpi4-fails.txt

@@ -418,7 +418,5 @@ dEQP-VK.api.external.semaphore.sync_fd.info_timeline,Fail
 
 dEQP-VK.draw.renderpass.inverted_depth_ranges.nodepthclamp_deltazero,Fail
 
-dEQP-VK.graphicsfuzz.cov-dfdx-dfdy-after-nested-loops,Fail
-
 # Works if using V3D_DEBUG=noloopunroll
 dEQP-VK.graphicsfuzz.cov-loop-condition-clamp-vec-of-ones,Crash

src/broadcom/compiler/vir_register_allocate.c

@@ -343,10 +343,14 @@ v3d_emit_spill_tmua(struct v3d_compile *c,
         struct qreg offset = vir_uniform_ui(c, spill_offset);
         add_node(c, offset.index, CLASS_BITS_ANY);
 
-        struct qinst *inst =
-                vir_ADD_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
-                             c->spill_base, offset);
+        /* We always enable per-quad on spills/fills to ensure we spill
+         * any channels involved with helper invocations.
+         */
+        struct qreg tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
+        struct qinst *inst = vir_ADD_dest(c, tmua, c->spill_base, offset);
         inst->qpu.flags.ac = cond;
+        inst->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
+                                              0xffffff7f); /* per-quad */
 
         vir_emit_thrsw(c);