From 58a5de5c346b78211500a26d338b4c0dc64fe760 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 30 Jan 2023 06:33:30 -0500 Subject: [PATCH] amd: add gfx12 register definitions into the register header generator MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The generator renamed some definitions to resolve conflicts. Reviewed-by: Samuel Pitoiset Acked-by: Timur Kristóf Acked-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/amd/common/ac_nir_lower_resinfo.c | 10 +-- src/amd/common/meson.build | 2 + .../compiler/aco_instruction_selection.cpp | 4 +- src/amd/compiler/aco_spill.cpp | 2 +- .../nir/radv_nir_apply_pipeline_layout.c | 6 +- src/amd/vulkan/radv_buffer_view.c | 3 +- src/amd/vulkan/radv_cmd_buffer.c | 31 +++++---- src/amd/vulkan/radv_descriptor_set.c | 7 +- src/amd/vulkan/radv_device.c | 2 +- src/amd/vulkan/radv_image_view.c | 27 ++++---- src/amd/vulkan/radv_queue.c | 68 +++++++++++-------- src/amd/vulkan/radv_sampler.c | 4 +- src/amd/vulkan/radv_shader.c | 6 +- src/amd/vulkan/radv_sqtt.c | 5 +- .../drivers/radeonsi/ci/radeonsi-run-tests.py | 2 +- src/gallium/drivers/radeonsi/si_compute.c | 8 +-- src/gallium/drivers/radeonsi/si_descriptors.c | 12 ++-- .../drivers/radeonsi/si_nir_lower_abi.c | 8 +-- .../drivers/radeonsi/si_nir_lower_resource.c | 4 +- src/gallium/drivers/radeonsi/si_sqtt.c | 2 +- src/gallium/drivers/radeonsi/si_state.c | 30 ++++---- .../drivers/radeonsi/si_state_viewport.c | 4 +- 22 files changed, 132 insertions(+), 115 deletions(-) diff --git a/src/amd/common/ac_nir_lower_resinfo.c b/src/amd/common/ac_nir_lower_resinfo.c index ea81ebbe9c5..0637ea3c775 100644 --- a/src/amd/common/ac_nir_lower_resinfo.c +++ b/src/amd/common/ac_nir_lower_resinfo.c @@ -29,7 +29,7 @@ static nir_def *query_samples(nir_builder *b, nir_def *desc, enum glsl_sampler_d if (dim == GLSL_SAMPLER_DIM_MS) { /* LAST_LEVEL contains log2(num_samples). */ - samples = get_field(b, desc, 3, ~C_00A00C_LAST_LEVEL); + samples = get_field(b, desc, 3, ~C_00A00C_LAST_LEVEL_GFX10); samples = nir_ishl(b, nir_imm_int(b, 1), samples); } else { samples = nir_imm_int(b, 1); @@ -41,7 +41,7 @@ static nir_def *query_samples(nir_builder *b, nir_def *desc, enum glsl_sampler_d static nir_def *query_levels(nir_builder *b, nir_def *desc) { nir_def *base_level = get_field(b, desc, 3, ~C_00A00C_BASE_LEVEL); - nir_def *last_level = get_field(b, desc, 3, ~C_00A00C_LAST_LEVEL); + nir_def *last_level = get_field(b, desc, 3, ~C_00A00C_LAST_LEVEL_GFX10); nir_def *levels = nir_iadd_imm(b, nir_isub(b, last_level, base_level), 1); @@ -86,10 +86,10 @@ lower_query_size(nir_builder *b, nir_def *desc, nir_src *lod, if (has_height) height = get_field(b, desc, 2, ~C_00A008_HEIGHT); if (has_depth) - depth = get_field(b, desc, 4, ~C_00A010_DEPTH); + depth = get_field(b, desc, 4, ~C_00A010_DEPTH_GFX10); if (is_array) { - last_array = get_field(b, desc, 4, ~C_00A010_DEPTH); + last_array = get_field(b, desc, 4, ~C_00A010_DEPTH_GFX10); base_array = get_field(b, desc, 4, ~C_00A010_BASE_ARRAY); } } else { @@ -168,7 +168,7 @@ lower_query_size(nir_builder *b, nir_def *desc, nir_src *lod, nir_def *uav3d = nir_ieq_imm(b, get_field(b, desc, 5, ~C_00A014_ARRAY_PITCH), 1); nir_def *layers_3d = - nir_isub(b, get_field(b, desc, 4, ~C_00A010_DEPTH), + nir_isub(b, get_field(b, desc, 4, ~C_00A010_DEPTH_GFX10), get_field(b, desc, 4, ~C_00A010_BASE_ARRAY)); layers_3d = nir_iadd_imm(b, layers_3d, 1); depth = nir_bcsel(b, uav3d, layers_3d, depth); diff --git a/src/amd/common/meson.build b/src/amd/common/meson.build index e4e8d4b23d4..1b135cbe677 100644 --- a/src/amd/common/meson.build +++ b/src/amd/common/meson.build @@ -30,11 +30,13 @@ amd_json_files = [ '../registers/gfx103.json', '../registers/gfx11.json', '../registers/gfx115.json', + '../registers/gfx12.json', # Manually written: '../registers/pkt3.json', '../registers/gfx10-rsrc.json', '../registers/gfx11-rsrc.json', + '../registers/gfx12-rsrc.json', '../registers/registers-manually-defined.json', ] diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index bde0d8cc031..54d4df710ca 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -5982,7 +5982,7 @@ visit_load_constant(isel_context* ctx, nir_intrinsic_instr* instr) S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); if (ctx->options->gfx_level >= GFX10) { - desc_type |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | + desc_type |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(ctx->options->gfx_level < GFX11); } else { @@ -7591,7 +7591,7 @@ get_scratch_resource(isel_context* ctx) S_008F0C_ADD_TID_ENABLE(1) | S_008F0C_INDEX_STRIDE(ctx->program->wave_size == 64 ? 3 : 2); if (ctx->program->gfx_level >= GFX10) { - rsrc_conf |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | + rsrc_conf |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(ctx->program->gfx_level < GFX11); } else if (ctx->program->gfx_level <= diff --git a/src/amd/compiler/aco_spill.cpp b/src/amd/compiler/aco_spill.cpp index a3bf09b4145..36d8ffdb574 100644 --- a/src/amd/compiler/aco_spill.cpp +++ b/src/amd/compiler/aco_spill.cpp @@ -1203,7 +1203,7 @@ load_scratch_resource(spill_ctx& ctx, Builder& bld, bool apply_scratch_offset) S_008F0C_ADD_TID_ENABLE(1) | S_008F0C_INDEX_STRIDE(ctx.program->wave_size == 64 ? 3 : 2); if (ctx.program->gfx_level >= GFX10) { - rsrc_conf |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | + rsrc_conf |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(ctx.program->gfx_level < GFX11); } else if (ctx.program->gfx_level <= GFX7) { diff --git a/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c b/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c index 196e9ba3470..9246323542b 100644 --- a/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c +++ b/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c @@ -141,10 +141,10 @@ load_inline_buffer_descriptor(nir_builder *b, apply_layout_state *state, nir_def uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); if (state->gfx_level >= GFX11) { - desc_type |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW); + desc_type |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW); } else if (state->gfx_level >= GFX10) { - desc_type |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | - S_008F0C_RESOURCE_LEVEL(1); + desc_type |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_FLOAT) | + S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1); } else { desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32); diff --git a/src/amd/vulkan/radv_buffer_view.c b/src/amd/vulkan/radv_buffer_view.c index 4f89fe967b7..90b589f6231 100644 --- a/src/amd/vulkan/radv_buffer_view.c +++ b/src/amd/vulkan/radv_buffer_view.c @@ -68,7 +68,8 @@ radv_make_texel_buffer_descriptor(struct radv_device *device, uint64_t va, VkFor * else: * offset+payload > NUM_RECORDS */ - rsrc_word3 |= S_008F0C_FORMAT(fmt->img_format) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET) | + rsrc_word3 |= S_008F0C_FORMAT_GFX10(fmt->img_format) | + S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET) | S_008F0C_RESOURCE_LEVEL(pdev->info.gfx_level < GFX11); } else { num_format = radv_translate_buffer_numformat(desc, first_non_void); diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index d7d677f1390..941ddd4345a 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2120,8 +2120,8 @@ radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer) VkRect2D viewport_scissor = radv_scissor_from_viewport(d->vk.vp.viewports + i); VkRect2D scissor = radv_intersect_scissor(&d->vk.vp.scissors[i], &viewport_scissor); - radeon_emit( - cs, S_028250_TL_X(scissor.offset.x) | S_028250_TL_Y(scissor.offset.y) | S_028250_WINDOW_OFFSET_DISABLE(1)); + radeon_emit(cs, S_028250_TL_X(scissor.offset.x) | S_028250_TL_Y_GFX6(scissor.offset.y) | + S_028250_WINDOW_OFFSET_DISABLE(1)); radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) | S_028254_BR_Y(scissor.offset.y + scissor.extent.height)); } @@ -4939,7 +4939,7 @@ radv_write_vertex_descriptors(const struct radv_cmd_buffer *cmd_buffer, const st unsigned hw_format = vtx_info->hw_format[vtx_info->num_channels - 1]; if (chip >= GFX10) { - rsrc_word3 = vtx_info->dst_sel | S_008F0C_FORMAT(hw_format); + rsrc_word3 = vtx_info->dst_sel | S_008F0C_FORMAT_GFX10(hw_format); } else { rsrc_word3 = vtx_info->dst_sel | S_008F0C_NUM_FORMAT((hw_format >> 4) & 0x7) | S_008F0C_DATA_FORMAT(hw_format & 0xf); @@ -4948,7 +4948,7 @@ radv_write_vertex_descriptors(const struct radv_cmd_buffer *cmd_buffer, const st rsrc_word3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); if (chip >= GFX10) - rsrc_word3 |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_UINT); + rsrc_word3 |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_UINT); else rsrc_word3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) | S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32); @@ -5174,9 +5174,9 @@ radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer) if (pdev->info.gfx_level >= GFX11) { rsrc_word3 |= - S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW); + S_008F0C_FORMAT_GFX10(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW); } else if (pdev->info.gfx_level >= GFX10) { - rsrc_word3 |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | + rsrc_word3 |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1); } else { rsrc_word3 |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32); @@ -6355,9 +6355,10 @@ radv_bind_descriptor_sets(struct radv_cmd_buffer *cmd_buffer, S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); if (pdev->info.gfx_level >= GFX11) { - dst[3] |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW); + dst[3] |= + S_008F0C_FORMAT_GFX10(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW); } else if (pdev->info.gfx_level >= GFX10) { - dst[3] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | + dst[3] |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1); } else { dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | @@ -8357,7 +8358,7 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe radeon_check_space(device->ws, cmd_buffer->cs, 6); radeon_set_context_reg(cmd_buffer->cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, - S_028204_TL_X(render->area.offset.x) | S_028204_TL_Y(render->area.offset.y)); + S_028204_TL_X(render->area.offset.x) | S_028204_TL_Y_GFX6(render->area.offset.y)); radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR, S_028208_BR_X(render->area.offset.x + render->area.extent.width) | S_028208_BR_Y(render->area.offset.y + render->area.extent.height)); @@ -10501,9 +10502,9 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, const struct radv if (info->unaligned) { radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3); - radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0])); - radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1])); - radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2])); + radeon_emit(cs, S_00B81C_NUM_THREAD_FULL_GFX6(compute_shader->info.cs.block_size[0])); + radeon_emit(cs, S_00B81C_NUM_THREAD_FULL_GFX6(compute_shader->info.cs.block_size[1])); + radeon_emit(cs, S_00B81C_NUM_THREAD_FULL_GFX6(compute_shader->info.cs.block_size[2])); dispatch_initiator |= S_00B800_USE_THREAD_DIMENSIONS(1); } @@ -10603,9 +10604,9 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, const struct radv } radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3); - radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) | S_00B81C_NUM_THREAD_PARTIAL(remainder[0])); - radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) | S_00B81C_NUM_THREAD_PARTIAL(remainder[1])); - radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) | S_00B81C_NUM_THREAD_PARTIAL(remainder[2])); + radeon_emit(cs, S_00B81C_NUM_THREAD_FULL_GFX6(cs_block_size[0]) | S_00B81C_NUM_THREAD_PARTIAL(remainder[0])); + radeon_emit(cs, S_00B81C_NUM_THREAD_FULL_GFX6(cs_block_size[1]) | S_00B81C_NUM_THREAD_PARTIAL(remainder[1])); + radeon_emit(cs, S_00B81C_NUM_THREAD_FULL_GFX6(cs_block_size[2]) | S_00B81C_NUM_THREAD_PARTIAL(remainder[2])); dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1); } diff --git a/src/amd/vulkan/radv_descriptor_set.c b/src/amd/vulkan/radv_descriptor_set.c index 525679157a7..0c145336848 100644 --- a/src/amd/vulkan/radv_descriptor_set.c +++ b/src/amd/vulkan/radv_descriptor_set.c @@ -1081,10 +1081,11 @@ write_buffer_descriptor(struct radv_device *device, unsigned *dst, uint64_t va, S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); if (pdev->info.gfx_level >= GFX11) { - rsrc_word3 |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW); + rsrc_word3 |= + S_008F0C_FORMAT_GFX10(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW); } else if (pdev->info.gfx_level >= GFX10) { - rsrc_word3 |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | - S_008F0C_RESOURCE_LEVEL(1); + rsrc_word3 |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_FLOAT) | + S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1); } else { rsrc_word3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32); diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 533072b139e..7d598981ffd 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -1911,7 +1911,7 @@ radv_initialise_ds_surface(const struct radv_device *device, struct radv_ds_buff ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.zs.stencil_epitch); } - ds->db_depth_view |= S_028008_MIPID(level); + ds->db_depth_view |= S_028008_MIPID_GFX9(level); ds->db_depth_size = S_02801C_X_MAX(iview->image->vk.extent.width - 1) | S_02801C_Y_MAX(iview->image->vk.extent.height - 1); diff --git a/src/amd/vulkan/radv_image_view.c b/src/amd/vulkan/radv_image_view.c index 77172bcec26..4cf17ed288d 100644 --- a/src/amd/vulkan/radv_image_view.c +++ b/src/amd/vulkan/radv_image_view.c @@ -154,9 +154,9 @@ radv_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image * if (plane->surface.blk_w == 2) pitch *= 2; - state[4] &= C_00A010_DEPTH & C_00A010_PITCH_MSB; - state[4] |= S_00A010_DEPTH(pitch - 1) | /* DEPTH contains low bits of PITCH. */ - S_00A010_PITCH_MSB((pitch - 1) >> 13); + state[4] &= C_00A010_DEPTH_GFX10 & C_00A010_PITCH_MSB_GFX103; + state[4] |= S_00A010_DEPTH_GFX10(pitch - 1) | /* DEPTH contains low bits of PITCH. */ + S_00A010_PITCH_MSB_GFX103((pitch - 1) >> 13); } if (gfx_level >= GFX10) { @@ -273,19 +273,19 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima depth = image->vk.array_layers / 6; state[0] = 0; - state[1] = S_00A004_FORMAT(img_format) | S_00A004_WIDTH_LO(width - 1); + state[1] = S_00A004_FORMAT_GFX10(img_format) | S_00A004_WIDTH_LO(width - 1); state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) | S_00A008_HEIGHT(height - 1) | S_00A008_RESOURCE_LEVEL(pdev->info.gfx_level < GFX11); state[3] = S_00A00C_DST_SEL_X(radv_map_swizzle(swizzle[0])) | S_00A00C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) | S_00A00C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) | S_00A00C_DST_SEL_W(radv_map_swizzle(swizzle[3])) | S_00A00C_BASE_LEVEL(image->vk.samples > 1 ? 0 : first_level) | - S_00A00C_LAST_LEVEL(image->vk.samples > 1 ? util_logbase2(image->vk.samples) : last_level) | + S_00A00C_LAST_LEVEL_GFX10(image->vk.samples > 1 ? util_logbase2(image->vk.samples) : last_level) | S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc)) | S_00A00C_TYPE(type); /* Depth is the the last accessible layer on gfx9+. The hw doesn't need * to know the total number of layers. */ state[4] = - S_00A010_DEPTH(type == V_008F1C_SQ_RSRC_IMG_3D ? depth - 1 : last_layer) | S_00A010_BASE_ARRAY(first_layer); + S_00A010_DEPTH_GFX10(type == V_008F1C_SQ_RSRC_IMG_3D ? depth - 1 : last_layer) | S_00A010_BASE_ARRAY(first_layer); state[5] = S_00A014_ARRAY_PITCH(0) | S_00A014_PERF_MOD(4); state[6] = 0; state[7] = 0; @@ -297,8 +297,8 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima * In SRV mode, BASE_ARRAY is ignored and DEPTH is the last slice of mipmap level 0. * In UAV mode, BASE_ARRAY is the first slice and DEPTH is the last slice of the bound level. */ - state[4] &= C_00A010_DEPTH; - state[4] |= S_00A010_DEPTH(!is_storage_image ? depth - 1 : u_minify(depth, first_level) - 1); + state[4] &= C_00A010_DEPTH_GFX10; + state[4] |= S_00A010_DEPTH_GFX10(!is_storage_image ? depth - 1 : u_minify(depth, first_level) - 1); state[5] |= S_00A014_ARRAY_PITCH(is_storage_image); } else if (sliced_3d) { unsigned total = u_minify(depth, first_level); @@ -312,7 +312,7 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima unsigned last_slice = first_slice + slice_count - 1; state[4] = 0; - state[4] |= S_00A010_DEPTH(last_slice) | S_00A010_BASE_ARRAY(first_slice); + state[4] |= S_00A010_DEPTH_GFX10(last_slice) | S_00A010_BASE_ARRAY(first_slice); state[5] |= S_00A014_ARRAY_PITCH(1); } @@ -322,8 +322,8 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima unsigned min_lod_clamped = util_unsigned_fixed(CLAMP(min_lod, 0, 15), 8); if (pdev->info.gfx_level >= GFX11) { - state[1] |= S_00A004_MAX_MIP(max_mip); - state[5] |= S_00A014_MIN_LOD_LO(min_lod_clamped); + state[1] |= S_00A004_MAX_MIP_GFX11(max_mip); + state[5] |= S_00A014_MIN_LOD_LO_GFX11(min_lod_clamped); state[6] |= S_00A018_MIN_LOD_HI(min_lod_clamped >> 5); } else { state[1] |= S_00A004_MIN_LOD(min_lod_clamped); @@ -367,7 +367,8 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima } fmask_state[0] = (va >> 8) | image->planes[0].surface.fmask_tile_swizzle; - fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) | S_00A004_FORMAT(format) | S_00A004_WIDTH_LO(width - 1); + fmask_state[1] = + S_00A004_BASE_ADDRESS_HI(va >> 40) | S_00A004_FORMAT_GFX10(format) | S_00A004_WIDTH_LO(width - 1); fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) | S_00A008_HEIGHT(height - 1) | S_00A008_RESOURCE_LEVEL(1); fmask_state[3] = @@ -375,7 +376,7 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) | S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) | S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.color.fmask_swizzle_mode) | S_00A00C_TYPE(radv_tex_dim(image->vk.image_type, view_type, image->vk.array_layers, 0, false, false)); - fmask_state[4] = S_00A010_DEPTH(last_layer) | S_00A010_BASE_ARRAY(first_layer); + fmask_state[4] = S_00A010_DEPTH_GFX10(last_layer) | S_00A010_BASE_ARRAY(first_layer); fmask_state[5] = 0; fmask_state[6] = S_00A018_META_PIPE_ALIGNED(1); fmask_state[7] = 0; diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c index c2b576599e5..8127403526a 100644 --- a/src/amd/vulkan/radv_queue.c +++ b/src/amd/vulkan/radv_queue.c @@ -273,9 +273,10 @@ radv_fill_shader_rings(struct radv_device *device, uint32_t *desc, struct radeon desc[1] |= S_008F04_SWIZZLE_ENABLE_GFX6(1); if (pdev->info.gfx_level >= GFX11) { - desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED); + desc[3] |= + S_008F0C_FORMAT_GFX10(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED); } else if (pdev->info.gfx_level >= GFX10) { - desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | + desc[3] |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | S_008F0C_RESOURCE_LEVEL(1); } else if (pdev->info.gfx_level >= GFX8) { /* DATA_FORMAT is STRIDE[14:17] for MUBUF with ADD_TID_ENABLE=1 */ @@ -296,9 +297,10 @@ radv_fill_shader_rings(struct radv_device *device, uint32_t *desc, struct radeon S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); if (pdev->info.gfx_level >= GFX11) { - desc[7] |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED); + desc[7] |= + S_008F0C_FORMAT_GFX10(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED); } else if (pdev->info.gfx_level >= GFX10) { - desc[7] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | + desc[7] |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | S_008F0C_RESOURCE_LEVEL(1); } else { desc[7] |= @@ -321,9 +323,10 @@ radv_fill_shader_rings(struct radv_device *device, uint32_t *desc, struct radeon S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); if (pdev->info.gfx_level >= GFX11) { - desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED); + desc[3] |= + S_008F0C_FORMAT_GFX10(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED); } else if (pdev->info.gfx_level >= GFX10) { - desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | + desc[3] |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | S_008F0C_RESOURCE_LEVEL(1); } else { desc[3] |= @@ -346,9 +349,10 @@ radv_fill_shader_rings(struct radv_device *device, uint32_t *desc, struct radeon desc[5] |= S_008F04_SWIZZLE_ENABLE_GFX6(1); if (pdev->info.gfx_level >= GFX11) { - desc[7] |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED); + desc[7] |= + S_008F0C_FORMAT_GFX10(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED); } else if (pdev->info.gfx_level >= GFX10) { - desc[7] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | + desc[7] |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | S_008F0C_RESOURCE_LEVEL(1); } else if (pdev->info.gfx_level >= GFX8) { /* DATA_FORMAT is STRIDE[14:17] for MUBUF with ADD_TID_ENABLE=1 */ @@ -373,10 +377,11 @@ radv_fill_shader_rings(struct radv_device *device, uint32_t *desc, struct radeon S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); if (pdev->info.gfx_level >= GFX11) { - desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW); + desc[3] |= + S_008F0C_FORMAT_GFX10(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW); } else if (pdev->info.gfx_level >= GFX10) { - desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | - S_008F0C_RESOURCE_LEVEL(1); + desc[3] |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_FLOAT) | + S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1); } else { desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32); @@ -389,10 +394,11 @@ radv_fill_shader_rings(struct radv_device *device, uint32_t *desc, struct radeon S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); if (pdev->info.gfx_level >= GFX11) { - desc[7] |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW); + desc[7] |= + S_008F0C_FORMAT_GFX10(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW); } else if (pdev->info.gfx_level >= GFX10) { - desc[7] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | - S_008F0C_RESOURCE_LEVEL(1); + desc[7] |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_FLOAT) | + S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1); } else { desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32); @@ -413,11 +419,12 @@ radv_fill_shader_rings(struct radv_device *device, uint32_t *desc, struct radeon S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); if (pdev->info.gfx_level >= GFX11) { - desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_UINT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED); + desc[3] |= + S_008F0C_FORMAT_GFX10(V_008F0C_GFX11_FORMAT_32_UINT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED); } else { assert(pdev->info.gfx_level >= GFX10_3); - desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_UINT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | - S_008F0C_RESOURCE_LEVEL(1); + desc[3] |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_UINT) | + S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | S_008F0C_RESOURCE_LEVEL(1); } desc[4] = task_payload_ring_va; @@ -427,11 +434,12 @@ radv_fill_shader_rings(struct radv_device *device, uint32_t *desc, struct radeon S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); if (pdev->info.gfx_level >= GFX11) { - desc[7] |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_UINT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED); + desc[7] |= + S_008F0C_FORMAT_GFX10(V_008F0C_GFX11_FORMAT_32_UINT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED); } else { assert(pdev->info.gfx_level >= GFX10_3); - desc[7] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_UINT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | - S_008F0C_RESOURCE_LEVEL(1); + desc[7] |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_UINT) | + S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | S_008F0C_RESOURCE_LEVEL(1); } } @@ -447,11 +455,12 @@ radv_fill_shader_rings(struct radv_device *device, uint32_t *desc, struct radeon S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); if (pdev->info.gfx_level >= GFX11) { - desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_UINT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED); + desc[3] |= + S_008F0C_FORMAT_GFX10(V_008F0C_GFX11_FORMAT_32_UINT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED); } else { assert(pdev->info.gfx_level >= GFX10_3); - desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_UINT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | - S_008F0C_RESOURCE_LEVEL(1); + desc[3] |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_UINT) | + S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | S_008F0C_RESOURCE_LEVEL(1); } } @@ -467,7 +476,8 @@ radv_fill_shader_rings(struct radv_device *device, uint32_t *desc, struct radeon desc[2] = attr_ring_size; desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) | - S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_32_32_32_FLOAT) | S_008F0C_INDEX_STRIDE(2) /* 32 elements */; + S_008F0C_FORMAT_GFX10(V_008F0C_GFX11_FORMAT_32_32_32_32_FLOAT) | + S_008F0C_INDEX_STRIDE(2) /* 32 elements */; } desc += 4; @@ -790,7 +800,7 @@ radv_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs) * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */ for (unsigned i = 0; i < 2; ++i) { unsigned cu_mask = i < gpu_info->num_se ? gpu_info->spi_cu_en : 0x0; - radeon_emit(cs, S_00B8AC_SA0_CU_EN(cu_mask) | S_00B8AC_SA1_CU_EN(cu_mask)); + radeon_emit(cs, S_00B88C_SA0_CU_EN(cu_mask) | S_00B88C_SA1_CU_EN(cu_mask)); } if (pdev->info.gfx_level >= GFX7) { @@ -798,7 +808,7 @@ radv_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs) radeon_set_sh_reg_seq(cs, R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2); for (unsigned i = 2; i < 4; ++i) { unsigned cu_mask = i < gpu_info->num_se ? gpu_info->spi_cu_en : 0x0; - radeon_emit(cs, S_00B8AC_SA0_CU_EN(cu_mask) | S_00B8AC_SA1_CU_EN(cu_mask)); + radeon_emit(cs, S_00B88C_SA0_CU_EN(cu_mask) | S_00B88C_SA1_CU_EN(cu_mask)); } if (device->border_color_data.bo) { @@ -851,7 +861,7 @@ radv_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs) /* SE4-SE7 */ for (unsigned i = 4; i < 8; ++i) { unsigned cu_mask = i < gpu_info->num_se ? gpu_info->spi_cu_en : 0x0; - radeon_emit(cs, S_00B8AC_SA0_CU_EN(cu_mask) | S_00B8AC_SA1_CU_EN(cu_mask)); + radeon_emit(cs, S_00B88C_SA0_CU_EN(cu_mask) | S_00B88C_SA1_CU_EN(cu_mask)); } radeon_set_sh_reg(cs, R_00B8BC_COMPUTE_DISPATCH_INTERLEAVE, 64); @@ -1101,8 +1111,8 @@ radv_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) } radeon_set_sh_reg_idx(pdev, cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, 3, - ac_apply_cu_en(S_00B01C_CU_EN(cu_mask_ps) | S_00B01C_WAVE_LIMIT(0x3F) | - S_00B01C_LDS_GROUP_SIZE(pdev->info.gfx_level >= GFX11), + ac_apply_cu_en(S_00B01C_CU_EN(cu_mask_ps) | S_00B01C_WAVE_LIMIT_GFX7(0x3F) | + S_00B01C_LDS_GROUP_SIZE_GFX11(pdev->info.gfx_level >= GFX11), C_00B01C_CU_EN, 0, &pdev->info)); } diff --git a/src/amd/vulkan/radv_sampler.c b/src/amd/vulkan/radv_sampler.c index ff525f9a54b..c1f8f4a53ba 100644 --- a/src/amd/vulkan/radv_sampler.c +++ b/src/amd/vulkan/radv_sampler.c @@ -225,8 +225,8 @@ radv_init_sampler(struct radv_device *device, struct radv_sampler *sampler, cons S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) | S_008F30_ANISO_BIAS(max_aniso_ratio) | S_008F30_DISABLE_CUBE_WRAP(disable_cube_wrap) | S_008F30_COMPAT_MODE(compat_mode) | S_008F30_FILTER_MODE(filter_mode) | S_008F30_TRUNC_COORD(trunc_coord)); - sampler->state[1] = (S_008F34_MIN_LOD(util_unsigned_fixed(CLAMP(pCreateInfo->minLod, 0, 15), 8)) | - S_008F34_MAX_LOD(util_unsigned_fixed(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) | + sampler->state[1] = (S_008F34_MIN_LOD_GFX6(util_unsigned_fixed(CLAMP(pCreateInfo->minLod, 0, 15), 8)) | + S_008F34_MAX_LOD_GFX6(util_unsigned_fixed(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) | S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0)); sampler->state[2] = (S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) | S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) | diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 565084d08f6..36e21a9ebc2 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -1688,9 +1688,9 @@ radv_precompute_registers_hw_cs(struct radv_device *device, struct radv_shader_b struct radv_shader_info *info = &binary->info; info->regs.cs.compute_resource_limits = radv_get_compute_resource_limits(pdev, info); - info->regs.cs.compute_num_thread_x = S_00B81C_NUM_THREAD_FULL(info->cs.block_size[0]); - info->regs.cs.compute_num_thread_y = S_00B81C_NUM_THREAD_FULL(info->cs.block_size[1]); - info->regs.cs.compute_num_thread_z = S_00B81C_NUM_THREAD_FULL(info->cs.block_size[2]); + info->regs.cs.compute_num_thread_x = S_00B81C_NUM_THREAD_FULL_GFX6(info->cs.block_size[0]); + info->regs.cs.compute_num_thread_y = S_00B81C_NUM_THREAD_FULL_GFX6(info->cs.block_size[1]); + info->regs.cs.compute_num_thread_z = S_00B81C_NUM_THREAD_FULL_GFX6(info->cs.block_size[2]); } static void diff --git a/src/amd/vulkan/radv_sqtt.c b/src/amd/vulkan/radv_sqtt.c index 4610717b90f..104efa47ef1 100644 --- a/src/amd/vulkan/radv_sqtt.c +++ b/src/amd/vulkan/radv_sqtt.c @@ -35,7 +35,8 @@ radv_sqtt_queue_events_enabled(void) static uint32_t gfx11_get_sqtt_ctrl(const struct radv_device *device, bool enable) { - return S_0367B0_MODE(enable) | S_0367B0_HIWATER(5) | S_0367B0_UTIL_TIMER(1) | S_0367B0_RT_FREQ(2) | /* 4096 clk */ + return S_0367B0_MODE(enable) | S_0367B0_HIWATER(5) | S_0367B0_UTIL_TIMER_GFX11(1) | + S_0367B0_RT_FREQ(2) | /* 4096 clk */ S_0367B0_DRAW_EVENT_EN(1) | S_0367B0_SPI_STALL_EN(1) | S_0367B0_SQ_STALL_EN(1) | S_0367B0_REG_AT_HWM(2); } @@ -135,7 +136,7 @@ radv_emit_sqtt_start(const struct radv_device *device, struct radeon_cmdbuf *cs, V_0367B8_TOKEN_EXCLUDE_VALUINST | V_0367B8_TOKEN_EXCLUDE_IMMEDIATE | V_0367B8_TOKEN_EXCLUDE_INST; } - sqtt_token_mask |= S_0367B8_TOKEN_EXCLUDE(token_exclude) | S_0367B8_BOP_EVENTS_TOKEN_INCLUDE(1); + sqtt_token_mask |= S_0367B8_TOKEN_EXCLUDE_GFX11(token_exclude) | S_0367B8_BOP_EVENTS_TOKEN_INCLUDE_GFX11(1); radeon_set_perfctr_reg(gfx_level, qf, cs, R_0367B8_SQ_THREAD_TRACE_TOKEN_MASK, sqtt_token_mask); diff --git a/src/gallium/drivers/radeonsi/ci/radeonsi-run-tests.py b/src/gallium/drivers/radeonsi/ci/radeonsi-run-tests.py index ef4eed10400..00d535e897b 100755 --- a/src/gallium/drivers/radeonsi/ci/radeonsi-run-tests.py +++ b/src/gallium/drivers/radeonsi/ci/radeonsi-run-tests.py @@ -257,7 +257,7 @@ if not args.slow: def gfx_level_to_str(cl): - supported = ["gfx6", "gfx7", "gfx8", "gfx9", "gfx10", "gfx10_3", "gfx11"] + supported = ["gfx6", "gfx7", "gfx8", "gfx9", "gfx10", "gfx10_3", "gfx11", "gfx12"] if 8 <= cl and cl < 8 + len(supported): return supported[cl - 8] return supported[-1] diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index 264fe53d1ec..b855269ba1b 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -507,7 +507,7 @@ static bool si_switch_compute_shader(struct si_context *sctx, struct si_compute SI_TRACKED_COMPUTE_PGM_RSRC2, rsrc2); gfx11_opt_push_compute_sh_reg(R_00B8A0_COMPUTE_PGM_RSRC3, SI_TRACKED_COMPUTE_PGM_RSRC3, - S_00B8A0_INST_PREF_SIZE(si_get_shader_prefetch_size(shader))); + S_00B8A0_INST_PREF_SIZE_GFX11(si_get_shader_prefetch_size(shader))); gfx11_opt_push_compute_sh_reg(R_00B860_COMPUTE_TMPRING_SIZE, SI_TRACKED_COMPUTE_TMPRING_SIZE, tmpring_size); if (shader->scratch_bo) { @@ -539,7 +539,7 @@ static bool si_switch_compute_shader(struct si_context *sctx, struct si_compute if (sctx->gfx_level >= GFX11) { radeon_opt_set_sh_reg(sctx, R_00B8A0_COMPUTE_PGM_RSRC3, SI_TRACKED_COMPUTE_PGM_RSRC3, - S_00B8A0_INST_PREF_SIZE(si_get_shader_prefetch_size(shader))); + S_00B8A0_INST_PREF_SIZE_GFX11(si_get_shader_prefetch_size(shader))); } radeon_end(); } @@ -830,8 +830,8 @@ static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_ bool partial_block_en = last_block[0] || last_block[1] || last_block[2]; uint32_t num_threads[3]; - num_threads[0] = S_00B81C_NUM_THREAD_FULL(info->block[0]); - num_threads[1] = S_00B820_NUM_THREAD_FULL(info->block[1]); + num_threads[0] = S_00B81C_NUM_THREAD_FULL_GFX6(info->block[0]); + num_threads[1] = S_00B820_NUM_THREAD_FULL_GFX6(info->block[1]); num_threads[2] = S_00B824_NUM_THREAD_FULL(info->block[2]); if (partial_block_en) { diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 5423c529d62..241478517f6 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -341,8 +341,8 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture if (tex->surface.blk_w == 2) pitch *= 2; - state[4] |= S_00A010_DEPTH(pitch - 1) | /* DEPTH contains low bits of PITCH. */ - S_00A010_PITCH_MSB((pitch - 1) >> 13); + state[4] |= S_00A010_DEPTH_GFX10(pitch - 1) | /* DEPTH contains low bits of PITCH. */ + S_00A010_PITCH_MSB_GFX103((pitch - 1) >> 13); } if (meta_va) { @@ -1133,10 +1133,10 @@ static void si_init_buffer_resources(struct si_context *sctx, S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); if (sctx->gfx_level >= GFX11) { - desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) | + desc[3] |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW); } else if (sctx->gfx_level >= GFX10) { - desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | + desc[3] |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1); } else { desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | @@ -1585,10 +1585,10 @@ void si_set_ring_buffer(struct si_context *sctx, uint slot, struct pipe_resource } if (sctx->gfx_level >= GFX11) { - desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) | + desc[3] |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED); } else if (sctx->gfx_level >= GFX10) { - desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | + desc[3] |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | S_008F0C_RESOURCE_LEVEL(1); } else { desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | diff --git a/src/gallium/drivers/radeonsi/si_nir_lower_abi.c b/src/gallium/drivers/radeonsi/si_nir_lower_abi.c index 01238a1ca25..cf6a113d484 100644 --- a/src/gallium/drivers/radeonsi/si_nir_lower_abi.c +++ b/src/gallium/drivers/radeonsi/si_nir_lower_abi.c @@ -54,7 +54,7 @@ static nir_def *build_attr_ring_desc(nir_builder *b, struct si_shader *shader, S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) | - S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_32_32_32_FLOAT) | + S_008F0C_FORMAT_GFX10(V_008F0C_GFX11_FORMAT_32_32_32_32_FLOAT) | S_008F0C_INDEX_STRIDE(2) /* 32 elements */), }; @@ -139,10 +139,10 @@ static nir_def *build_tess_ring_desc(nir_builder *b, struct si_screen *screen, S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); if (screen->info.gfx_level >= GFX11) { - rsrc3 |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) | + rsrc3 |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW); } else if (screen->info.gfx_level >= GFX10) { - rsrc3 |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | + rsrc3 |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1); } else { @@ -234,7 +234,7 @@ static void build_gsvs_ring_desc(nir_builder *b, struct lower_abi_state *s) if (sel->screen->info.gfx_level >= GFX10) { rsrc3 |= - S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | + S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | S_008F0C_RESOURCE_LEVEL(1); } else { diff --git a/src/gallium/drivers/radeonsi/si_nir_lower_resource.c b/src/gallium/drivers/radeonsi/si_nir_lower_resource.c index 5ee7603acdb..08a668b7c0f 100644 --- a/src/gallium/drivers/radeonsi/si_nir_lower_resource.c +++ b/src/gallium/drivers/radeonsi/si_nir_lower_resource.c @@ -36,10 +36,10 @@ static nir_def *load_ubo_desc_fast_path(nir_builder *b, nir_def *addr_lo, S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); if (sel->screen->info.gfx_level >= GFX11) - rsrc3 |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) | + rsrc3 |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW); else if (sel->screen->info.gfx_level >= GFX10) - rsrc3 |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | + rsrc3 |= S_008F0C_FORMAT_GFX10(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1); else rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | diff --git a/src/gallium/drivers/radeonsi/si_sqtt.c b/src/gallium/drivers/radeonsi/si_sqtt.c index 335107dff17..d8f2ab9b630 100644 --- a/src/gallium/drivers/radeonsi/si_sqtt.c +++ b/src/gallium/drivers/radeonsi/si_sqtt.c @@ -98,7 +98,7 @@ static void si_emit_sqtt_start(struct si_context *sctx, S_0367B4_SA_SEL(0) | S_0367B4_WGP_SEL(wgp) | S_0367B4_SIMD_SEL(0)); radeon_emit(S_0367B8_REG_INCLUDE(token_mask) | - S_0367B8_TOKEN_EXCLUDE(V_008D18_TOKEN_EXCLUDE_PERF)); + S_0367B8_TOKEN_EXCLUDE_GFX11(V_008D18_TOKEN_EXCLUDE_PERF)); } else { radeon_set_privileged_config_reg( R_008D04_SQ_THREAD_TRACE_BUF0_SIZE, diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 67099b1e366..f35eca7928d 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2818,7 +2818,7 @@ static void si_init_depth_surface(struct si_context *sctx, struct si_surface *su surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.epitch); surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.zs.stencil_epitch); } - surf->db_depth_view |= S_028008_MIPID(level); + surf->db_depth_view |= S_028008_MIPID_GFX9(level); surf->db_depth_size = S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) | S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1); @@ -4252,7 +4252,7 @@ void si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf * else: * offset+payload > NUM_RECORDS */ - state[7] |= S_008F0C_FORMAT(fmt->img_format) | + state[7] |= S_008F0C_FORMAT_GFX10(fmt->img_format) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET) | S_008F0C_RESOURCE_LEVEL(screen->info.gfx_level < GFX11); } else { @@ -4372,7 +4372,7 @@ static void cdna_emu_make_image_descriptor(struct si_screen *screen, struct si_t if (screen->info.gfx_level >= GFX10) { const struct gfx10_format *fmt = &ac_get_gfx10_format_table(&screen->info)[pipe_format]; - state[3] |= S_008F0C_FORMAT(fmt->img_format) | + state[3] |= S_008F0C_FORMAT_GFX10(fmt->img_format) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET) | S_008F0C_RESOURCE_LEVEL(screen->info.gfx_level < GFX11); } else { @@ -4476,7 +4476,7 @@ static void gfx10_make_texture_descriptor( depth = res->array_size / 6; state[0] = 0; - state[1] = S_00A004_FORMAT(img_format) | S_00A004_WIDTH_LO(width - 1); + state[1] = S_00A004_FORMAT_GFX10(img_format) | S_00A004_WIDTH_LO(width - 1); state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) | S_00A008_HEIGHT(height - 1) | S_00A008_RESOURCE_LEVEL(screen->info.gfx_level < GFX11); @@ -4486,13 +4486,13 @@ static void gfx10_make_texture_descriptor( S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle[2])) | S_00A00C_DST_SEL_W(si_map_swizzle(swizzle[3])) | S_00A00C_BASE_LEVEL(res->nr_samples > 1 ? 0 : first_level) | - S_00A00C_LAST_LEVEL(res->nr_samples > 1 ? util_logbase2(res->nr_samples) : last_level) | + S_00A00C_LAST_LEVEL_GFX10(res->nr_samples > 1 ? util_logbase2(res->nr_samples) : last_level) | S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc->swizzle)) | S_00A00C_TYPE(type); /* Depth is the the last accessible layer on gfx9+. The hw doesn't need * to know the total number of layers. */ state[4] = - S_00A010_DEPTH((type == V_008F1C_SQ_RSRC_IMG_3D && sampler) ? depth - 1 : last_layer) | + S_00A010_DEPTH_GFX10((type == V_008F1C_SQ_RSRC_IMG_3D && sampler) ? depth - 1 : last_layer) | S_00A010_BASE_ARRAY(first_layer); state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D && !sampler)) | S_00A014_PERF_MOD(4); @@ -4501,7 +4501,7 @@ static void gfx10_make_texture_descriptor( tex->buffer.b.b.last_level; if (screen->info.gfx_level >= GFX11) { - state[1] |= S_00A004_MAX_MIP(max_mip); + state[1] |= S_00A004_MAX_MIP_GFX11(max_mip); } else { state[5] |= S_00A014_MAX_MIP(max_mip); } @@ -4566,7 +4566,7 @@ static void gfx10_make_texture_descriptor( } #undef FMASK fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle; - fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) | S_00A004_FORMAT(format) | + fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) | S_00A004_FORMAT_GFX10(format) | S_00A004_WIDTH_LO(width - 1); fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) | S_00A008_HEIGHT(height - 1) | S_00A008_RESOURCE_LEVEL(1); @@ -4575,7 +4575,7 @@ static void gfx10_make_texture_descriptor( S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) | S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) | S_00A00C_SW_MODE(tex->surface.u.gfx9.color.fmask_swizzle_mode) | S_00A00C_TYPE(si_tex_dim(screen, tex, target, 0)); - fmask_state[4] = S_00A010_DEPTH(last_layer) | S_00A010_BASE_ARRAY(first_layer); + fmask_state[4] = S_00A010_DEPTH_GFX10(last_layer) | S_00A010_BASE_ARRAY(first_layer); fmask_state[5] = 0; fmask_state[6] = S_00A018_META_PIPE_ALIGNED(1); fmask_state[7] = 0; @@ -5179,8 +5179,8 @@ static void *si_create_sampler_state(struct pipe_context *ctx, S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) | S_008F30_ANISO_BIAS(max_aniso_ratio) | S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) | S_008F30_TRUNC_COORD(trunc_coord)); - rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) | - S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) | + rstate->val[1] = (S_008F34_MIN_LOD_GFX6(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) | + S_008F34_MAX_LOD_GFX6(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) | S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0)); rstate->val[2] = (S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) | S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) | @@ -5472,7 +5472,7 @@ static void *si_create_vertex_elements(struct pipe_context *ctx, unsigned count, ASSERTED unsigned last_vertex_format = sscreen->info.gfx_level >= GFX11 ? 64 : 128; assert(fmt->img_format != 0 && fmt->img_format < last_vertex_format); v->elem[i].rsrc_word3 |= - S_008F0C_FORMAT(fmt->img_format) | + S_008F0C_FORMAT_GFX10(fmt->img_format) | S_008F0C_RESOURCE_LEVEL(sscreen->info.gfx_level < GFX11) | /* OOB_SELECT chooses the out-of-bounds check: * - 1: index >= NUM_RECORDS (Structured) @@ -6079,7 +6079,7 @@ static void gfx6_init_gfx_preamble_state(struct si_context *sctx) if (sctx->gfx_level >= GFX7) { si_pm4_set_reg_idx3(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, ac_apply_cu_en(S_00B01C_CU_EN(0xffffffff) | - S_00B01C_WAVE_LIMIT(0x3F), + S_00B01C_WAVE_LIMIT_GFX7(0x3F), C_00B01C_CU_EN, 0, &sscreen->info)); } @@ -6326,8 +6326,8 @@ static void gfx10_init_gfx_preamble_state(struct si_context *sctx) } si_pm4_set_reg_idx3(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, ac_apply_cu_en(S_00B01C_CU_EN(cu_mask_ps) | - S_00B01C_WAVE_LIMIT(0x3F) | - S_00B01C_LDS_GROUP_SIZE(sctx->gfx_level >= GFX11), + S_00B01C_WAVE_LIMIT_GFX7(0x3F) | + S_00B01C_LDS_GROUP_SIZE_GFX11(sctx->gfx_level >= GFX11), C_00B01C_CU_EN, 0, &sscreen->info)); si_pm4_set_reg(pm4, R_00B0C0_SPI_SHADER_REQ_CTRL_PS, S_00B0C0_SOFT_GROUPING_EN(1) | diff --git a/src/gallium/drivers/radeonsi/si_state_viewport.c b/src/gallium/drivers/radeonsi/si_state_viewport.c index 15e05d7dfcd..92f0878cafb 100644 --- a/src/gallium/drivers/radeonsi/si_state_viewport.c +++ b/src/gallium/drivers/radeonsi/si_state_viewport.c @@ -239,10 +239,10 @@ static void si_emit_one_scissor(struct si_context *ctx, struct radeon_cmdbuf *cs * any_scissor.BR_X/Y <= 0. */ if (ctx->gfx_level == GFX6 && (final.maxx == 0 || final.maxy == 0)) { - radeon_emit(S_028250_TL_X(1) | S_028250_TL_Y(1) | S_028250_WINDOW_OFFSET_DISABLE(1)); + radeon_emit(S_028250_TL_X(1) | S_028250_TL_Y_GFX6(1) | S_028250_WINDOW_OFFSET_DISABLE(1)); radeon_emit(S_028254_BR_X(1) | S_028254_BR_Y(1)); } else { - radeon_emit(S_028250_TL_X(final.minx) | S_028250_TL_Y(final.miny) | + radeon_emit(S_028250_TL_X(final.minx) | S_028250_TL_Y_GFX6(final.miny) | S_028250_WINDOW_OFFSET_DISABLE(1)); radeon_emit(S_028254_BR_X(final.maxx) | S_028254_BR_Y(final.maxy)); }