diff --git a/src/imagination/vulkan/pvr_formats.c b/src/imagination/vulkan/pvr_formats.c
index 203fb76d5cc..67dd1651d20 100644
--- a/src/imagination/vulkan/pvr_formats.c
+++ b/src/imagination/vulkan/pvr_formats.c
@@ -113,6 +113,8 @@ static const struct pvr_format pvr_format_table[] = {
    FORMAT(R8G8_UINT, U8U8, U8U8, UINT8),
    /* VK_FORMAT_R8G8_SINT = 21. */
    FORMAT(R8G8_SINT, S8S8, S8S8, SINT8),
+   /* VK_FORMAT_R8G8B8_UINT = 27. */
+   FORMAT(R8G8B8_UINT, U8U8U8, U8U8U8, UINT8),
    /* VK_FORMAT_R8G8B8A8_UNORM = 37. */
    FORMAT(R8G8B8A8_UNORM, U8U8U8U8, U8U8U8U8, U8),
    /* VK_FORMAT_R8G8B8A8_SNORM = 38. */
@@ -171,6 +173,10 @@ static const struct pvr_format pvr_format_table[] = {
    FORMAT(R16G16_SINT, S16S16, S16S16, SINT16),
    /* VK_FORMAT_R16G16_SFLOAT = 83. */
    FORMAT(R16G16_SFLOAT, F16F16, F16F16, F16),
+   /* VK_FORMAT_R16G16B16_SNORM = 85. */
+   FORMAT(R16G16B16_SNORM, S16S16S16, S16S16S16, S16),
+   /* VK_FORMAT_R16G16B16_SINT = 89. */
+   FORMAT(R16G16B16_SINT, S16S16S16, S16S16S16, SINT16),
    /* VK_FORMAT_R16G16B16A16_UNORM = 91. */
    FORMAT(R16G16B16A16_UNORM, U16U16U16U16, U16U16U16U16, U16),
    /* VK_FORMAT_R16G16B16A16_SNORM = 92. */
@@ -285,11 +291,13 @@ static const struct pvr_tex_format_table_entry {
    /*  28 */ FORMAT(F16F16F16F16, NONE, R16G16B16A16_FLOAT),
    /*  29 */ FORMAT(U16U16U16U16, R16G16B16A16_UINT, R16G16B16A16_UNORM),
    /*  30 */ FORMAT(S16S16S16S16, R16G16B16A16_SINT, R16G16B16A16_SNORM),
+   /*  33 */ FORMAT(S16S16S16, R16G16B16_SINT, R16G16B16_SNORM),
    /*  34 */ FORMAT(F32F32, NONE, R32G32_FLOAT),
    /*  35 */ FORMAT(U32U32, R32G32_UINT, R32G32_UNORM),
    /*  36 */ FORMAT(S32S32, R32G32_SINT, R32G32_SNORM),
    /*  38 */ FORMAT(X24X8F32, NONE, Z32_FLOAT_S8X24_UINT),
    /*  39 */ FORMAT(X24G8X32, X32_S8X24_UINT, NONE),
+   /*  58 */ FORMAT(U8U8U8, R8G8B8_UINT, R8G8B8_UNORM),
    /*  61 */ FORMAT(F32F32F32F32, NONE, R32G32B32A32_FLOAT),
    /*  62 */ FORMAT(U32U32U32U32, R32G32B32A32_UINT, R32G32B32A32_UNORM),
    /*  63 */ FORMAT(S32S32S32S32, R32G32B32A32_SINT, R32G32B32A32_SNORM),