diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log
index 098aed2d504..2558a4dd290 100644
--- a/src/freedreno/.gitlab-ci/reference/crash.log
+++ b/src/freedreno/.gitlab-ci/reference/crash.log
@@ -163,7 +163,7 @@ registers:
 	00000000	0x30: 00000000
 	00000000	0x31: 00000000
 	00000000	0x32: 00000000
-	03d0e242	RBBM_INT_0_MASK: 0x3d0e242
+	03d0e242	RBBM_INT_0_MASK: { CP_AHB_ERROR | RBBM_ATB_ASYNCFIFO_OVERFLOW | CP_HW_ERROR | CP_IB2 | CP_IB1 | CP_RB | CP_CACHE_FLUSH_TS | RBBM_ATB_BUS_OVERFLOW | RBBM_HANG_DETECT | UCHE_OOB_ACCESS | UCHE_TRAP_INTR }
 	00000000	0x39: 00000000
 	00000010	0x3a: 00000010
 	00000000	0x3b: 00000000
@@ -628,7 +628,7 @@ registers:
 	80000000	0x813: 80000000
 	00000000	0x820: 00000000
 	00000000	CP_HW_FAULT: 0
-	00000000	CP_INTERRUPT_STATUS: 0
+	00000000	CP_INTERRUPT_STATUS: { 0 }
 	00000000	CP_PROTECT_STATUS: 0
 	00000707	0x826: 00000707
 	00000001	0x827: 00000001
diff --git a/src/freedreno/.gitlab-ci/reference/crash_prefetch.log b/src/freedreno/.gitlab-ci/reference/crash_prefetch.log
index a3c53b36c43..da99307fdbf 100644
--- a/src/freedreno/.gitlab-ci/reference/crash_prefetch.log
+++ b/src/freedreno/.gitlab-ci/reference/crash_prefetch.log
@@ -330,7 +330,7 @@ registers:
 	00000003	GBIF_HALT_ACK: 0x3
 	00000000	0x3c47: 00000000
 	00000000	GBIF_PERF_PWR_CNT_EN: 0
-	00000000	0x3cc1: 00000000
+	00000000	GBIF_PERF_PWR_CNT_CLR: 0
 	00000000	GBIF_PERF_CNT_SEL: 0
 	00000000	GBIF_PERF_PWR_CNT_SEL: 0
 	00000000	GBIF_PERF_CNT_LOW0: 0
@@ -378,7 +378,7 @@ registers:
 	00000000	0x30: 00000000
 	00000000	0x31: 00000000
 	00000000	0x32: 00000000
-	03d0e242	RBBM_INT_0_MASK: 0x3d0e242
+	03d0e242	RBBM_INT_0_MASK: { CP_AHB_ERROR | RBBM_ATB_ASYNCFIFO_OVERFLOW | CP_HW_ERROR | CP_IB2 | CP_IB1 | CP_RB | CP_CACHE_FLUSH_TS | RBBM_ATB_BUS_OVERFLOW | RBBM_HANG_DETECT | UCHE_OOB_ACCESS | UCHE_TRAP_INTR }
 	00000000	0x39: 00000000
 	00000010	0x3a: 00000010
 	00000000	0x3b: 00000000
@@ -843,7 +843,7 @@ registers:
 	80000000	0x813: 80000000
 	00000001	0x820: 00000001
 	00000000	CP_HW_FAULT: 0
-	00000000	CP_INTERRUPT_STATUS: 0
+	00000000	CP_INTERRUPT_STATUS: { 0 }
 	00000000	CP_PROTECT_STATUS: 0
 	0908261e	0x826: 0908261e
 	00000001	0x827: 00000001
diff --git a/src/freedreno/.gitlab-ci/reference/prefetch-test.log b/src/freedreno/.gitlab-ci/reference/prefetch-test.log
index d6977c0ea63..7ae2bffa58e 100644
--- a/src/freedreno/.gitlab-ci/reference/prefetch-test.log
+++ b/src/freedreno/.gitlab-ci/reference/prefetch-test.log
@@ -909,7 +909,7 @@ registers:
 	00000003	GBIF_HALT_ACK: 0x3
 	00000000	0x3c47: 00000000
 	00000000	GBIF_PERF_PWR_CNT_EN: 0
-	00000000	0x3cc1: 00000000
+	00000000	GBIF_PERF_PWR_CNT_CLR: 0
 	00000000	GBIF_PERF_CNT_SEL: 0
 	00000000	GBIF_PERF_PWR_CNT_SEL: 0
 	00000000	GBIF_PERF_CNT_LOW0: 0
@@ -957,7 +957,7 @@ registers:
 	00000000	0x30: 00000000
 	00000000	0x31: 00000000
 	00000000	0x32: 00000000
-	03d0e242	RBBM_INT_0_MASK: 0x3d0e242
+	03d0e242	RBBM_INT_0_MASK: { CP_AHB_ERROR | RBBM_ATB_ASYNCFIFO_OVERFLOW | CP_HW_ERROR | CP_IB2 | CP_IB1 | CP_RB | CP_CACHE_FLUSH_TS | RBBM_ATB_BUS_OVERFLOW | RBBM_HANG_DETECT | UCHE_OOB_ACCESS | UCHE_TRAP_INTR }
 	00000000	0x39: 00000000
 	00000010	0x3a: 00000010
 	00000000	0x3b: 00000000
@@ -1422,7 +1422,7 @@ registers:
 	80000000	0x813: 80000000
 	0012d6ac	0x820: 0012d6ac
 	00000000	CP_HW_FAULT: 0
-	00000000	CP_INTERRUPT_STATUS: 0
+	00000000	CP_INTERRUPT_STATUS: { 0 }
 	00000000	CP_PROTECT_STATUS: 0
 	5050f1f1	0x826: 5050f1f1
 	00000001	0x827: 00000001
diff --git a/src/freedreno/registers/adreno.xml b/src/freedreno/registers/adreno.xml
index 7df6db4a5d3..92b7f37a721 100644
--- a/src/freedreno/registers/adreno.xml
+++ b/src/freedreno/registers/adreno.xml
@@ -10,7 +10,6 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 <import file="adreno/a5xx.xml"/>
 <import file="adreno/a6xx.xml"/>
 <import file="adreno/a6xx_gmu.xml"/>
-<import file="adreno/a7xx.xml"/>
 <import file="adreno/ocmem.xml"/>
 <import file="adreno/adreno_control_regs.xml"/>
 <import file="adreno/adreno_pipe_regs.xml"/>
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index 571fcabf55e..702e7a03a27 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -958,10 +958,12 @@ to upconvert to 32b float internally?
 	<value value="0x3" name="A6XX_INVALID_ZTEST"/>
 </enum>
 
-<domain name="A6XX" width="32">
-	<bitset name="A6XX_RBBM_INT_0_MASK" inline="no">
+<domain name="A6XX" width="32" prefix="variant" varset="chip">
+	<bitset name="A6XX_RBBM_INT_0_MASK" inline="no" varset="chip">
 		<bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
 		<bitfield name="CP_AHB_ERROR" pos="1" type="boolean"/>
+		<bitfield name="CP_IPC_INTR_0" pos="4" type="boolean" variants="A7XX"/>
+		<bitfield name="CP_IPC_INTR_1" pos="5" type="boolean" variants="A7XX"/>
 		<bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6" type="boolean"/>
 		<bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/>
 		<bitfield name="CP_SW" pos="8" type="boolean"/>
@@ -971,21 +973,30 @@ to upconvert to 32b float internally?
 		<bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/>
 		<bitfield name="CP_IB2" pos="13" type="boolean"/>
 		<bitfield name="CP_IB1" pos="14" type="boolean"/>
-		<bitfield name="CP_RB" pos="15" type="boolean"/>
+		<bitfield name="CP_RB" pos="15" type="boolean" variants="A6XX"/>
+		<!-- Same as above but different name??: -->
+		<bitfield name="PM4CPINTERRUPT" pos="15" type="boolean" variants="A7XX"/>
+		<bitfield name="PM4CPINTERRUPTLPAC" pos="16" type="boolean" variants="A7XX"/>
 		<bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
 		<bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/>
 		<bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/>
+		<bitfield name="CP_CACHE_FLUSH_TS_LPAC" pos="21" type="boolean" variants="A7XX"/>
 		<bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/>
 		<bitfield name="RBBM_HANG_DETECT" pos="23" type="boolean"/>
 		<bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/>
 		<bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/>
 		<bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/>
 		<bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/>
+		<bitfield name="TSBWRITEERROR" pos="28" type="boolean" variants="A7XX"/>
 		<bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/>
 		<bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/>
 	</bitset>
 
-	<bitset name="A6XX_CP_INT">
+	<!--
+		Note the _LPAC bits probably *actually* first appeared in a660, but the
+		_BV bits are new in a7xx
+	 -->
+	<bitset name="A6XX_CP_INT" varset="chip">
 		<bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/>
 		<bitfield name="CP_UCODE_ERROR" pos="1" type="boolean"/>
 		<bitfield name="CP_HW_FAULT_ERROR" pos="2" type="boolean"/>
@@ -993,6 +1004,16 @@ to upconvert to 32b float internally?
 		<bitfield name="CP_AHB_ERROR" pos="5" type="boolean"/>
 		<bitfield name="CP_VSD_PARITY_ERROR" pos="6" type="boolean"/>
 		<bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7" type="boolean"/>
+		<bitfield name="CP_OPCODE_ERROR_LPAC" pos="8" type="boolean" variants="A7XX"/>
+		<bitfield name="CP_UCODE_ERROR_LPAC" pos="9" type="boolean" variants="A7XX"/>
+		<bitfield name="CP_HW_FAULT_ERROR_LPAC" pos="10" type="boolean" variants="A7XX"/>
+		<bitfield name="CP_REGISTER_PROTECTION_ERROR_LPAC" pos="11" type="boolean" variants="A7XX"/>
+		<bitfield name="CP_ILLEGAL_INSTR_ERROR_LPAC" pos="12" type="boolean" variants="A7XX"/>
+		<bitfield name="CP_OPCODE_ERROR_BV" pos="13" type="boolean" variants="A7XX"/>
+		<bitfield name="CP_UCODE_ERROR_BV" pos="14" type="boolean" variants="A7XX"/>
+		<bitfield name="CP_HW_FAULT_ERROR_BV" pos="15" type="boolean" variants="A7XX"/>
+		<bitfield name="CP_REGISTER_PROTECTION_ERROR_BV" pos="16" type="boolean" variants="A7XX"/>
+		<bitfield name="CP_ILLEGAL_INSTR_ERROR_BV" pos="17" type="boolean" variants="A7XX"/>
 	</bitset>
 
 	<reg64 offset="0x0800" name="CP_RB_BASE"/>
@@ -1005,7 +1026,7 @@ to upconvert to 32b float internally?
 		<bitfield name="IFPC" pos="0" type="boolean"/>
 	</reg32>
 	<reg32 offset="0x0821" name="CP_HW_FAULT"/>
-	<reg32 offset="0x0823" name="CP_INTERRUPT_STATUS"/>
+	<reg32 offset="0x0823" name="CP_INTERRUPT_STATUS" type="A6XX_CP_INT"/>
 	<reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
 	<reg32 offset="0x0825" name="CP_STATUS_1"/>
 	<reg64 offset="0x0830" name="CP_SQE_INSTR_BASE"/>
@@ -1060,7 +1081,9 @@ to upconvert to 32b float internally?
 	<reg64 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/>
 	<reg64 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/>
 	<reg64 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR"/>
+	<reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A7XX"/>
 	<array offset="0x08D0" name="CP_PERFCTR_CP_SEL" stride="1" length="14"/>
+	<array offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7" variants="A7XX"/>
 	<reg64 offset="0x0900" name="CP_CRASH_SCRIPT_BASE"/>
 	<reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
 	<reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
@@ -1135,7 +1158,39 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x098D" name="CP_AHB_CNTL"/>
 	<reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/>
 	<reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD"/>
+
+	<reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS" variants="A7XX"/>
+	<reg32 offset="0x0a64" name="CP_BV_HW_FAULT" variants="A7XX"/>
+	<reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR" variants="A7XX"/>
+	<reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA" variants="A7XX"/>
+	<reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR" variants="A7XX"/>
+	<reg32 offset="0x0a84" name="CP_BV_ROQ_DBG_DATA" variants="A7XX"/>
+	<reg32 offset="0x0a85" name="CP_BV_SQE_UCODE_DBG_ADDR" variants="A7XX"/>
+	<reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA" variants="A7XX"/>
+	<reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR" variants="A7XX"/>
+	<reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA" variants="A7XX"/>
+	<reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR" variants="A7XX"/>
+	<reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA" variants="A7XX"/>
+	<reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR" variants="A7XX"/>
+
+	<reg32 offset="0x0a9a" name="CP_RESOURCE_TBL_DBG_ADDR" variants="A7XX"/>
+	<reg32 offset="0x0a9b" name="CP_RESOURCE_TBL_DBG_DATA" variants="A7XX"/>
+	<reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL" variants="A7XX"/>
+	<reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG" variants="A7XX"/>
+
+	<reg32 offset="0x0b0a" name="CP_LPAC_DRAW_STATE_ADDR" variants="A7XX"/>
+	<reg32 offset="0x0b0b" name="CP_LPAC_DRAW_STATE_DATA" variants="A7XX"/>
+	<reg32 offset="0x0b0c" name="CP_LPAC_ROQ_DBG_ADDR" variants="A7XX"/>
+	<reg32 offset="0x0b27" name="CP_SQE_AC_UCODE_DBG_ADDR" variants="A7XX"/>
+	<reg32 offset="0x0b28" name="CP_SQE_AC_UCODE_DBG_DATA" variants="A7XX"/>
+	<reg32 offset="0x0b29" name="CP_SQE_AC_STAT_ADDR" variants="A7XX"/>
+	<reg32 offset="0x0b2a" name="CP_SQE_AC_STAT_DATA" variants="A7XX"/>
+
+	<reg32 offset="0x0b31" name="CP_LPAC_APRIV_CNTL" variants="A7XX"/>
 	<reg32 offset="0x0B34" name="CP_LPAC_PROG_FIFO_SIZE"/>
+	<reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA" variants="A7XX"/>
+	<reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA" variants="A7XX"/>
+	<reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR" variants="A7XX"/>
 	<reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE"/>
 	<reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
 	<reg32 offset="0x0018" name="RBBM_GPR0_CNTL"/>
@@ -1172,22 +1227,60 @@ to upconvert to 32b float internally?
 		<bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
 	</reg32>
 	<reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
-	<array offset="0x0400" name="RBBM_PERFCTR_CP" stride="2" length="14"/>
-	<array offset="0x041c" name="RBBM_PERFCTR_RBBM" stride="2" length="4"/>
-	<array offset="0x0424" name="RBBM_PERFCTR_PC" stride="2" length="8"/>
-	<array offset="0x0434" name="RBBM_PERFCTR_VFD" stride="2" length="8"/>
-	<array offset="0x0444" name="RBBM_PERFCTR_HLSQ" stride="2" length="6"/>
-	<array offset="0x0450" name="RBBM_PERFCTR_VPC" stride="2" length="6"/>
-	<array offset="0x045c" name="RBBM_PERFCTR_CCU" stride="2" length="5"/>
-	<array offset="0x0466" name="RBBM_PERFCTR_TSE" stride="2" length="4"/>
-	<array offset="0x046e" name="RBBM_PERFCTR_RAS" stride="2" length="4"/>
-	<array offset="0x0476" name="RBBM_PERFCTR_UCHE" stride="2" length="12"/>
-	<array offset="0x048e" name="RBBM_PERFCTR_TP" stride="2" length="12"/>
-	<array offset="0x04a6" name="RBBM_PERFCTR_SP" stride="2" length="24"/>
-	<array offset="0x04d6" name="RBBM_PERFCTR_RB" stride="2" length="8"/>
-	<array offset="0x04e6" name="RBBM_PERFCTR_VSC" stride="2" length="2"/>
-	<array offset="0x04ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4"/>
-	<array offset="0x04f2" name="RBBM_PERFCTR_CMP" stride="2" length="4"/>
+
+	<reg32 offset="0x0260" name="RBBM_CLOCK_MODE_CP" variants="A7XX"/>
+	<reg32 offset="0x0284" name="RBBM_CLOCK_MODE_BV_LRZ" variants="A7XX"/>
+	<reg32 offset="0x0285" name="RBBM_CLOCK_MODE_BV_GRAS" variants="A7XX"/>
+	<reg32 offset="0x0286" name="RBBM_CLOCK_MODE2_GRAS" variants="A7XX"/>
+	<reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD" variants="A7XX"/>
+	<reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC" variants="A7XX"/>
+
+	<array offset="0x0400" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A6XX"/>
+	<array offset="0x041c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A6XX"/>
+	<array offset="0x0424" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A6XX"/>
+	<array offset="0x0434" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A6XX"/>
+	<array offset="0x0444" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A6XX"/>
+	<array offset="0x0450" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A6XX"/>
+	<array offset="0x045c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A6XX"/>
+	<array offset="0x0466" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A6XX"/>
+	<array offset="0x046e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A6XX"/>
+	<array offset="0x0476" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A6XX"/>
+	<array offset="0x048e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A6XX"/>
+	<array offset="0x04a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A6XX"/>
+	<array offset="0x04d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A6XX"/>
+	<array offset="0x04e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A6XX"/>
+	<array offset="0x04ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A6XX"/>
+	<array offset="0x04f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A6XX"/>
+
+	<array offset="0x0300" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A7XX"/>
+	<array offset="0x031c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A7XX"/>
+	<array offset="0x0324" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A7XX"/>
+	<array offset="0x0334" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A7XX"/>
+	<array offset="0x0344" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A7XX"/>
+	<array offset="0x0350" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A7XX"/>
+	<array offset="0x035c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A7XX"/>
+	<array offset="0x0366" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A7XX"/>
+	<array offset="0x036e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A7XX"/>
+	<array offset="0x0376" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A7XX"/>
+	<array offset="0x038e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A7XX"/>
+	<array offset="0x03a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A7XX"/>
+	<array offset="0x03d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A7XX"/>
+	<array offset="0x03e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A7XX"/>
+	<array offset="0x03ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A7XX"/>
+	<array offset="0x03f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A7XX"/>
+	<array offset="0x03fa" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A7XX"/>
+	<array offset="0x0410" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A7XX"/>
+	<array offset="0x041c" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A7XX"/>
+	<array offset="0x042a" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A7XX"/>
+	<array offset="0x0442" name="RBBM_PERFCTR2_TP" stride="2" length="6" variants="A7XX"/>
+	<array offset="0x044e" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A7XX"/>
+	<array offset="0x0460" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A7XX"/>
+	<array offset="0x0470" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A7XX"/>
+	<array offset="0x0480" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A7XX"/>
+	<array offset="0x048c" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A7XX"/>
+	<array offset="0x0494" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A7XX"/>
+	<array offset="0x049c" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A7XX"/>
+
 	<reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
 	<reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
 	<reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
@@ -1200,6 +1293,8 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x050e" name="RBBM_PERFCTR_SRAM_INIT_CMD"/>
 	<reg32 offset="0x050f" name="RBBM_PERFCTR_SRAM_INIT_STATUS"/>
 	<reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
+	<reg32 offset="0x0534" name="RBBM_NC_MODE_CNTL" variants="A7XX"/>
+	<reg32 offset="0x0535" name="RBBM_SNAPSHOT_STATUS" variants="A7XX"/>
 
 	<!---
 	    This block of registers aren't tied to perf counters. They
@@ -1235,6 +1330,7 @@ to upconvert to 32b float internally?
 	<reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
 	<reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>
 	<reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+	<reg64 offset="0xfc00" name="RBBM_SECVID_TSB_STATUS" variants="A7XX"/>
 	<reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
 	<reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/>
 	<reg32 offset="0x00016" name="RBBM_GBIF_HALT"/>
@@ -1242,9 +1338,13 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD">
 		<bitfield pos="0" name="WAIT_GPU_IDLE" type="boolean"/>
 	</reg32>
+
+	<reg32 offset="0x00016" name="RBBM_GBIF_HALT" variants="A7XX"/>
+	<reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK" variants="A7XX"/>
 	<reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
 	<reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK"/>
-	<reg32 offset="0x00038" name="RBBM_INT_0_MASK"/>
+	<reg32 offset="0x00038" name="RBBM_INT_0_MASK" type="A6XX_RBBM_INT_0_MASK"/>
+	<reg32 offset="0x0003a" name="RBBM_INT_2_MASK" variants="A7XX"/>
 	<reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>
 	<reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>
 	<reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>
@@ -1474,6 +1574,7 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x3c45" name="GBIF_HALT"/>
 	<reg32 offset="0x3c46" name="GBIF_HALT_ACK"/>
 	<reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/>
+	<reg32 offset="0x3cc1" name="GBIF_PERF_PWR_CNT_CLR"/>
 	<reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/>
 	<reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/>
 	<reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/>
@@ -1961,6 +2062,7 @@ to upconvert to 32b float internally?
 		<bitfield name="LRZCACHELOCKDIS" pos="11" type="boolean"/>
 	</reg32>
 	<reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
+	<reg32 offset="0x8602" name="GRAS_NC_MODE_CNTL" variants="A7XX"/>
 	<array offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4"/>
 	<array offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4"/>
 	<array offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="4"/>
@@ -2423,6 +2525,7 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x8e28" name="RB_UNKNOWN_8E28" low="0" high="10"/>
 	<!-- 0x8e29-0x8e2b invalid -->
 	<array offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4"/>
+	<array offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A7XX"/>
 	<reg32 offset="0x8e3b" name="RB_RB_SUB_BLOCK_SEL_CNTL_HOST"/>
 	<reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
 	<!-- 0x8e3e-0x8e4f invalid -->
@@ -2602,7 +2705,8 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
 	<reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0"/> <!-- always 0x0 ? -->
 	<reg32 offset="0x9603" name="VPC_UNKNOWN_9603" low="0" high="26"/>
-	<array offset="0x9604" name="VPC_PERFCTR_VPC_SEL" stride="1" length="6"/>
+	<array offset="0x9604" name="VPC_PERFCTR_VPC_SEL" stride="1" length="6" variants="A6XX"/>
+	<array offset="0x960b" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12" variants="A7XX"/>
 	<!-- 0x960a-0x9623 invalid -->
 	<!-- TODO: regs from 0x9624-0x963a -->
 	<!-- 0x963b-0x97ff invalid -->
@@ -2789,7 +2893,8 @@ to upconvert to 32b float internally?
 		<bitfield name="OVERRIDE" pos="0" type="boolean"/>
 	</reg32>
 
-	<array offset="0x9e34" name="PC_PERFCTR_PC_SEL" stride="1" length="8"/>
+	<array offset="0x9e34" name="PC_PERFCTR_PC_SEL" stride="1" length="8" variants="A6XX"/>
+	<array offset="0x9e42" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A7XX"/>
 
 	<!-- always 0x0 -->
 	<reg32 offset="0x9e72" name="PC_UNKNOWN_9E72"/>
@@ -2882,7 +2987,8 @@ to upconvert to 32b float internally?
 	<reg32 offset="0xa0f8" name="VFD_POWER_CNTL" low="0" high="2"/>
 
 	<reg32 offset="0xa601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
-	<array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="8"/>
+	<array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="8" variants="A6XX"/>
+	<array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="16" variants="A7XX"/>
 
 	<!--
 	Note: this seems to always be paired with another bit in another
@@ -3486,6 +3592,9 @@ to upconvert to 32b float internally?
 		<bitfield name="CS" pos="5" type="boolean"/>
 	</reg32>
 	<array offset="0xae10" name="SP_PERFCTR_SP_SEL" stride="1" length="24"/>
+	<array offset="0xae60" name="SP_PERFCTR_HLSQ_SEL" stride="1" length="6" variants="A7XX"/>
+	<reg32 offset="0xae6d" name="SP_READ_SEL" variants="A7XX"/>
+	<array offset="0xae80" name="SP_PERFCTR_SP_SEL" stride="1" length="36" variants="A7XX"/>
 	<!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) -->
 	<!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range -->
 	<reg32 offset="0xbe22" name="SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>
@@ -3786,6 +3895,8 @@ to upconvert to 32b float internally?
 	<!-- TODO: some valid registers between 0xbe20 and 0xbe33 -->
 	<reg32 offset="0xbe22" name="HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>
 
+	<reg32 offset="0xc000" name="SP_AHB_READ_APERTURE" variants="A7XX"/>
+
 	<!--
 		These special registers signal the beginning/end of an event
 		sequence. The sequence used internally for an event looks like:
diff --git a/src/freedreno/registers/adreno/a6xx_gmu.xml b/src/freedreno/registers/adreno/a6xx_gmu.xml
index f8bf1fd2f62..a0f41c44b4a 100644
--- a/src/freedreno/registers/adreno/a6xx_gmu.xml
+++ b/src/freedreno/registers/adreno/a6xx_gmu.xml
@@ -4,7 +4,7 @@ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 <import file="freedreno_copyright.xml"/>
 
-<domain name="A6XX" width="32">
+<domain name="A6XX" width="32" prefix="variant" varset="chip">
 
 	<bitset name="A6XX_GMU_GPU_IDLE_STATUS">
 		<bitfield name="BUSY_IGN_AHB" pos="23"/>
diff --git a/src/freedreno/registers/adreno/a7xx.xml b/src/freedreno/registers/adreno/a7xx.xml
deleted file mode 100644
index f258f6467bb..00000000000
--- a/src/freedreno/registers/adreno/a7xx.xml
+++ /dev/null
@@ -1,346 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<database xmlns="http://nouveau.freedesktop.org/"
-xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
-xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
-<import file="freedreno_copyright.xml"/>
-<import file="adreno/adreno_common.xml"/>
-<import file="adreno/adreno_pm4.xml"/>
-
-<domain name="A7XX" width="32">
-	<reg32 offset="0x0011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/>
-	<reg32 offset="0x0016" name="RBBM_GBIF_HALT"/>
-	<reg32 offset="0x0017" name="RBBM_GBIF_HALT_ACK"/>
-	<reg32 offset="0x001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
-	<reg32 offset="0x0037" name="RBBM_INT_CLEAR_CMD"/>
-	<reg32 offset="0x0038" name="RBBM_INT_0_MASK">
-		<bitfield name="GPUIDLE" pos="0" type="boolean"/>
-		<bitfield name="AHBERROR" pos="1" type="boolean"/>
-		<bitfield name="CPIPCINT0" pos="4" type="boolean"/>
-		<bitfield name="CPIPCINT1" pos="5" type="boolean"/>
-		<bitfield name="ATBASYNCFIFOOVERFLOW" pos="6" type="boolean"/>
-		<bitfield name="GPCERROR" pos="7" type="boolean"/>
-		<bitfield name="SWINTERRUPT" pos="8" type="boolean"/>
-		<bitfield name="HWERROR" pos="9" type="boolean"/>
-		<bitfield name="CCU_CLEAN_DEPTH_TS" pos="10" type="boolean"/>
-		<bitfield name="CCU_CLEAN_COLOR_TS" pos="11" type="boolean"/>
-		<bitfield name="CCU_RESOLVE_CLEAN_TS" pos="12" type="boolean"/>
-		<bitfield name="PM4CPINTERRUPT" pos="15" type="boolean"/>
-		<bitfield name="PM4CPINTERRUPTLPAC" pos="16" type="boolean"/>
-		<bitfield name="RB_DONE_TS" pos="17" type="boolean"/>
-		<bitfield name="CACHE_CLEAN_TS" pos="20" type="boolean"/>
-		<bitfield name="CACHE_CLEAN_TS_LPAC" pos="21" type="boolean"/>
-		<bitfield name="ATBBUSOVERFLOW" pos="22" type="boolean"/>
-		<bitfield name="HANGDETECTINTERRUPT" pos="23" type="boolean"/>
-		<bitfield name="OUTOFBOUNDACCESS" pos="24" type="boolean"/>
-		<bitfield name="UCHETRAPINTERRUPT" pos="25" type="boolean"/>
-		<bitfield name="DEBUGBUSINTERRUPT0" pos="26" type="boolean"/>
-		<bitfield name="DEBUGBUSINTERRUPT1" pos="27" type="boolean"/>
-		<bitfield name="TSBWRITEERROR" pos="28" type="boolean"/>
-		<bitfield name="ISDBCPUIRQ" pos="30" type="boolean"/>
-		<bitfield name="ISDBUNDERDEBUG" pos="31" type="boolean"/>
-	</reg32>
-	<reg32 offset="0x003a" name="RBBM_INT_2_MASK"/>
-	<reg32 offset="0x0042" name="RBBM_SP_HYST_CNT"/>
-	<reg32 offset="0x0043" name="RBBM_SW_RESET_CMD"/>
-	<reg32 offset="0x0044" name="RBBM_RAC_THRESHOLD_CNT"/>
-	<reg32 offset="0x00ae" name="RBBM_CLOCK_CNTL"/>
-	<reg32 offset="0x00b0" name="RBBM_CLOCK_CNTL_SP0"/>
-	<reg32 offset="0x00b4" name="RBBM_CLOCK_CNTL2_SP0"/>
-	<reg32 offset="0x00b8" name="RBBM_CLOCK_DELAY_SP0"/>
-	<reg32 offset="0x00bc" name="RBBM_CLOCK_HYST_SP0"/>
-	<reg32 offset="0x00c0" name="RBBM_CLOCK_CNTL_TP0"/>
-	<reg32 offset="0x00c4" name="RBBM_CLOCK_CNTL2_TP0"/>
-	<reg32 offset="0x00c8" name="RBBM_CLOCK_CNTL3_TP0"/>
-	<reg32 offset="0x00cc" name="RBBM_CLOCK_CNTL4_TP0"/>
-	<reg32 offset="0x00d0" name="RBBM_CLOCK_DELAY_TP0"/>
-	<reg32 offset="0x00d4" name="RBBM_CLOCK_DELAY2_TP0"/>
-	<reg32 offset="0x00d8" name="RBBM_CLOCK_DELAY3_TP0"/>
-	<reg32 offset="0x00dc" name="RBBM_CLOCK_DELAY4_TP0"/>
-	<reg32 offset="0x00e0" name="RBBM_CLOCK_HYST_TP0"/>
-	<reg32 offset="0x00e4" name="RBBM_CLOCK_HYST2_TP0"/>
-	<reg32 offset="0x00e8" name="RBBM_CLOCK_HYST3_TP0"/>
-	<reg32 offset="0x00ec" name="RBBM_CLOCK_HYST4_TP0"/>
-	<reg32 offset="0x00f0" name="RBBM_CLOCK_CNTL_RB0"/>
-	<reg32 offset="0x00f4" name="RBBM_CLOCK_CNTL2_RB0"/>
-	<reg32 offset="0x00f8" name="RBBM_CLOCK_CNTL_CCU0"/>
-	<reg32 offset="0x0100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
-	<reg32 offset="0x0104" name="RBBM_CLOCK_CNTL_RAC"/>
-	<reg32 offset="0x0105" name="RBBM_CLOCK_CNTL2_RAC"/>
-	<reg32 offset="0x0106" name="RBBM_CLOCK_DELAY_RAC"/>
-	<reg32 offset="0x0107" name="RBBM_CLOCK_HYST_RAC"/>
-	<reg32 offset="0x0108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
-	<reg32 offset="0x0109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
-	<reg32 offset="0x010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
-	<reg32 offset="0x010b" name="RBBM_CLOCK_CNTL_UCHE"/>
-	<reg32 offset="0x010f" name="RBBM_CLOCK_DELAY_UCHE"/>
-	<reg32 offset="0x0110" name="RBBM_CLOCK_HYST_UCHE"/>
-	<reg32 offset="0x0111" name="RBBM_CLOCK_MODE_VFD"/>
-	<reg32 offset="0x0112" name="RBBM_CLOCK_DELAY_VFD"/>
-	<reg32 offset="0x0113" name="RBBM_CLOCK_HYST_VFD"/>
-	<reg32 offset="0x0114" name="RBBM_CLOCK_MODE_GPC"/>
-	<reg32 offset="0x0115" name="RBBM_CLOCK_DELAY_GPC"/>
-	<reg32 offset="0x0116" name="RBBM_CLOCK_HYST_GPC"/>
-	<reg32 offset="0x0117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
-	<reg32 offset="0x0118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
-	<reg32 offset="0x0119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
-	<reg32 offset="0x011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
-	<reg32 offset="0x011b" name="RBBM_CLOCK_MODE_HLSQ"/>
-	<reg32 offset="0x011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
-	<reg32 offset="0x011d" name="RBBM_CLOCK_HYST_HLSQ"/>
-	<reg32 offset="0x0201" name="RBBM_INT_0_STATUS"/>
-	<reg32 offset="0x0210" name="RBBM_STATUS">
-		<bitfield name="CPAHBBUSYCXMASTER" pos="0" type="boolean"/>
-		<bitfield name="CPAHBBUSYCPMASTER" pos="1" type="boolean"/>
-		<bitfield name="CPBUSY" pos="2" type="boolean"/>
-		<bitfield name="GFXDBGCBUSY" pos="3" type="boolean"/>
-		<bitfield name="VBIFGXFPARTBUSY" pos="4" type="boolean"/>
-		<bitfield name="TSEBUSY" pos="5" type="boolean"/>
-		<bitfield name="RASBUSY" pos="6" type="boolean"/>
-		<bitfield name="RBBUSY" pos="7" type="boolean"/>
-		<bitfield name="CCUBUSY" pos="8" type="boolean"/>
-		<bitfield name="A2DBUSY" pos="9" type="boolean"/>
-		<bitfield name="LRZBUSY" pos="10" type="boolean"/>
-		<bitfield name="COMDCOMBUSY" pos="11" type="boolean"/>
-		<bitfield name="PCDCALLBUSY" pos="12" type="boolean"/>
-		<bitfield name="PCVSDBUSY" pos="13" type="boolean"/>
-		<bitfield name="TESSBUSY" pos="14" type="boolean"/>
-		<bitfield name="VFDBUSY" pos="15" type="boolean"/>
-		<bitfield name="VPCBUSY" pos="16" type="boolean"/>
-		<bitfield name="UCHEBUSY" pos="17" type="boolean"/>
-		<bitfield name="SPBUSY" pos="18" type="boolean"/>
-		<bitfield name="TPL1BUSY" pos="19" type="boolean"/>
-		<bitfield name="VSCBUSY" pos="20" type="boolean"/>
-		<bitfield name="HLSQBUSY" pos="21" type="boolean"/>
-		<bitfield name="GPUBUSYIGNAHBCP" pos="22" type="boolean"/>
-		<bitfield name="GPUBUSYIGNAHB" pos="23" type="boolean"/>
-	</reg32>
-	<reg32 offset="0x0213" name="RBBM_STATUS3"/>
-	<reg32 offset="0x0260" name="RBBM_CLOCK_MODE_CP"/>
-	<reg32 offset="0x0284" name="RBBM_CLOCK_MODE_BV_LRZ"/>
-	<reg32 offset="0x0285" name="RBBM_CLOCK_MODE_BV_GRAS"/>
-	<reg32 offset="0x0286" name="RBBM_CLOCK_MODE2_GRAS"/>
-	<reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD"/>
-	<reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC"/>
-	<reg64 offset="0x0300" name="RBBM_PERFCTR_CP" stride="2" length="14"/>
-	<reg64 offset="0x031c" name="RBBM_PERFCTR_RBBM" stride="2" length="4"/>
-	<reg64 offset="0x0324" name="RBBM_PERFCTR_PC" stride="2" length="8"/>
-	<reg64 offset="0x0334" name="RBBM_PERFCTR_VFD" stride="2" length="8"/>
-	<reg64 offset="0x0344" name="RBBM_PERFCTR_HLSQ" stride="2" length="6"/>
-	<reg64 offset="0x0350" name="RBBM_PERFCTR_VPC" stride="2" length="6"/>
-	<reg64 offset="0x035c" name="RBBM_PERFCTR_CCU" stride="2" length="5"/>
-	<reg64 offset="0x0366" name="RBBM_PERFCTR_TSE" stride="2" length="4"/>
-	<reg64 offset="0x036e" name="RBBM_PERFCTR_RAS" stride="2" length="4"/>
-	<reg64 offset="0x0376" name="RBBM_PERFCTR_UCHE" stride="2" length="12"/>
-	<reg64 offset="0x038e" name="RBBM_PERFCTR_TP" stride="2" length="12"/>
-	<reg64 offset="0x03a6" name="RBBM_PERFCTR_SP" stride="2" length="24"/>
-	<reg64 offset="0x03d6" name="RBBM_PERFCTR_RB" stride="2" length="8"/>
-	<reg64 offset="0x03e6" name="RBBM_PERFCTR_VSC" stride="2" length="2"/>
-	<reg64 offset="0x03ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4"/>
-	<reg64 offset="0x03f2" name="RBBM_PERFCTR_CMP" stride="2" length="4"/>
-	<reg64 offset="0x03fa" name="RBBM_PERFCTR_UFC" stride="2" length="4"/>
-	<reg64 offset="0x0410" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6"/>
-	<reg64 offset="0x041c" name="RBBM_PERFCTR2_CP" stride="2" length="7"/>
-	<reg64 offset="0x042a" name="RBBM_PERFCTR2_SP" stride="2" length="12"/>
-	<reg64 offset="0x0442" name="RBBM_PERFCTR2_TP" stride="2" length="6"/>
-	<reg64 offset="0x044e" name="RBBM_PERFCTR2_UFC" stride="2" length="2"/>
-	<reg64 offset="0x0460" name="RBBM_PERFCTR_BV_PC" stride="2" length="8"/>
-	<reg64 offset="0x0470" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8"/>
-	<reg64 offset="0x0480" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6"/>
-	<reg64 offset="0x048c" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4"/>
-	<reg64 offset="0x0494" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4"/>
-	<reg64 offset="0x049c" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4"/>
-	<reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
-	<reg32 offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4"/>
-	<reg32 offset="0x050b" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
-	<reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
-	<reg32 offset="0x0534" name="RBBM_NC_MODE_CNTL"/>
-	<reg32 offset="0x0535" name="RBBM_SNAPSHOT_STATUS"/>
-	<reg64 offset="0x0800" name="CP_RB_BASE"/>
-	<reg32 offset="0x0802" name="CP_RB_CNTL"/>
-	<reg64 offset="0x0804" name="CP_RB_RPTR_ADDR"/>
-	<reg32 offset="0x0806" name="CP_RB_RPTR"/>
-	<reg32 offset="0x0807" name="CP_RB_WPTR"/>
-	<reg32 offset="0x0808" name="CP_SQE_CNTL"/>
-	<reg32 offset="0x0812" name="CP_CP2GMU_STATUS"/>
-	<reg32 offset="0x0821" name="CP_HW_FAULT"/>
-	<reg32 offset="0x0823" name="CP_INTERRUPT_STATUS">
-		<bitfield name="OPCODEERROR" pos="0" type="boolean"/>
-		<bitfield name="UCODEERROR" pos="1" type="boolean"/>
-		<bitfield name="CPHWFAULT" pos="2" type="boolean"/>
-		<bitfield name="REGISTERPROTECTION" pos="4" type="boolean"/>
-		<bitfield name="VSDPARITYERROR" pos="6" type="boolean"/>
-		<bitfield name="ILLEGALINSTRUCTION" pos="7" type="boolean"/>
-		<bitfield name="OPCODEERRORLPAC" pos="8" type="boolean"/>
-		<bitfield name="UCODEERRORLPAC" pos="9" type="boolean"/>
-		<bitfield name="CPHWFAULTLPAC" pos="10" type="boolean"/>
-		<bitfield name="REGISTERPROTECTIONLPAC" pos="11" type="boolean"/>
-		<bitfield name="ILLEGALINSTRUCTIONLPAC" pos="12" type="boolean"/>
-		<bitfield name="OPCODEERRORBV" pos="13" type="boolean"/>
-		<bitfield name="UCODEERRORBV" pos="14" type="boolean"/>
-		<bitfield name="CPHWFAULTBV" pos="15" type="boolean"/>
-		<bitfield name="REGISTERPROTECTIONBV" pos="16" type="boolean"/>
-		<bitfield name="ILLEGALINSTRUCTIONBV" pos="17" type="boolean"/>
-	</reg32>
-	<reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
-	<reg32 offset="0x0825" name="CP_STATUS_1"/>
-	<reg64 offset="0x0830" name="CP_SQE_INSTR_BASE"/>
-	<reg32 offset="0x0840" name="CP_MISC_CNTL"/>
-	<reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
-	<reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
-	<reg32 offset="0x0844" name="CP_APRIV_CNTL"/>
-	<reg32 offset="0x084f" name="CP_PROTECT_CNTL"/>
-	<reg32 offset="0x0850" name="CP_PROTECT_REG" stride="1" length="48"/>
-	<reg32 offset="0x08a0" name="CP_CONTEXT_SWITCH_CNTL"/>
-	<reg64 offset="0x08a1" name="CP_CONTEXT_SWITCH_SMMU_INFO"/>
-	<reg64 offset="0x08a3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/>
-	<reg64 offset="0x08a5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/>
-	<reg64 offset="0x08a7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR"/>
-	<reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS"/>
-	<reg32 offset="0x08d0" name="CP_PERFCTR_CP_SEL" stride="1" length="14"/>
-	<reg32 offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7"/>
-	<reg64 offset="0x0900" name="CP_CRASH_SCRIPT_BASE"/>
-	<reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
-	<reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
-	<reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
-	<reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
-	<reg32 offset="0x090a" name="CP_DRAW_STATE_ADDR"/>
-	<reg32 offset="0x090b" name="CP_DRAW_STATE_DATA"/>
-	<reg32 offset="0x090c" name="CP_ROQ_DBG_ADDR"/>
-	<reg32 offset="0x090d" name="CP_ROQ_DBG_DATA"/>
-	<reg32 offset="0x090e" name="CP_MEM_POOL_DBG_ADDR"/>
-	<reg32 offset="0x090f" name="CP_MEM_POOL_DBG_DATA"/>
-	<reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
-	<reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
-	<reg64 offset="0x0928" name="CP_IB1_BASE"/>
-	<reg32 offset="0x092a" name="CP_IB1_REM_SIZE"/>
-	<reg64 offset="0x092b" name="CP_IB2_BASE"/>
-	<reg32 offset="0x092d" name="CP_IB2_REM_SIZE"/>
-	<reg64 offset="0x0980" name="CP_ALWAYS_ON_COUNTER"/>
-	<reg32 offset="0x098d" name="CP_AHB_CNTL"/>
-	<reg32 offset="0x0a00" name="CP_APERTURE_CNTL_HOST"/>
-	<reg32 offset="0x0a03" name="CP_APERTURE_CNTL_CD"/>
-	<reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS"/>
-	<reg32 offset="0x0a64" name="CP_BV_HW_FAULT"/>
-	<reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR"/>
-	<reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA"/>
-	<reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR"/>
-	<reg32 offset="0x0a84" name="CP_BV_ROQ_DBG_DATA"/>
-	<reg32 offset="0x0a85" name="CP_BV_SQE_UCODE_DBG_ADDR"/>
-	<reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA"/>
-	<reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR"/>
-	<reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA"/>
-	<reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR"/>
-	<reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA"/>
-	<reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR"/>
-	<reg32 offset="0x0a9a" name="CP_RESOURCE_TBL_DBG_ADDR"/>
-	<reg32 offset="0x0a9b" name="CP_RESOURCE_TBL_DBG_DATA"/>
-	<reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL"/>
-	<reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG"/>
-	<reg32 offset="0x0b0a" name="CP_LPAC_DRAW_STATE_ADDR"/>
-	<reg32 offset="0x0b0b" name="CP_LPAC_DRAW_STATE_DATA"/>
-	<reg32 offset="0x0b0c" name="CP_LPAC_ROQ_DBG_ADDR"/>
-	<reg32 offset="0x0b27" name="CP_SQE_AC_UCODE_DBG_ADDR"/>
-	<reg32 offset="0x0b28" name="CP_SQE_AC_UCODE_DBG_DATA"/>
-	<reg32 offset="0x0b29" name="CP_SQE_AC_STAT_ADDR"/>
-	<reg32 offset="0x0b2a" name="CP_SQE_AC_STAT_DATA"/>
-	<reg32 offset="0x0b31" name="CP_LPAC_APRIV_CNTL"/>
-	<reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA"/>
-	<reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA"/>
-	<reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR"/>
-	<reg32 offset="0x0cd8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2"/>
-	<reg32 offset="0x0e01" name="UCHE_MODE_CNTL"/>
-	<reg64 offset="0x0e07" name="UCHE_WRITE_THRU_BASE"/>
-	<reg64 offset="0x0e09" name="UCHE_TRAP_BASE"/>
-	<reg64 offset="0x0e0b" name="UCHE_GMEM_RANGE_MIN"/>
-	<reg64 offset="0x0e0d" name="UCHE_GMEM_RANGE_MAX"/>
-	<reg32 offset="0x0e17" name="UCHE_CACHE_WAYS"/>
-	<reg32 offset="0x0e19" name="UCHE_CLIENT_PF"/>
-	<reg32 offset="0x0e1c" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12"/>
-	<reg32 offset="0x0e3a" name="UCHE_GBIF_GX_CONFIG"/>
-	<reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG"/>
-	<reg32 offset="0x1140" name="PDC_GPU_ENABLE_PDC"/>
-	<reg32 offset="0x1148" name="PDC_GPU_SEQ_START_ADDR"/>
-	<reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
-	<reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
-	<reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
-	<reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1"/>
-	<reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
-	<reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1"/>
-	<reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
-	<reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
-	<reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
-	<reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
-	<reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
-	<reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
-	<reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
-	<reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
-	<reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
-	<reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
-	<reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
-	<reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
-	<reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
-	<reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
-	<reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
-	<reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
-	<reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
-	<reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
-	<reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
-	<reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
-	<reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
-	<reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
-	<reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/>
-	<reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/>
-	<reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/>
-	<reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/>
-	<reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/>
-	<reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/>
-	<reg32 offset="0x3c45" name="GBIF_HALT"/>
-	<reg32 offset="0x3c46" name="GBIF_HALT_ACK"/>
-	<reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/>
-	<reg32 offset="0x3cc1" name="GBIF_PERF_PWR_CNT_CLR"/>
-	<reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/>
-	<reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/>
-	<reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/>
-	<reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/>
-	<reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/>
-	<reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/>
-	<reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/>
-	<reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/>
-	<reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/>
-	<reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/>
-	<reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/>
-	<reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/>
-	<reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/>
-	<reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/>
-	<reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/>
-	<reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/>
-	<reg32 offset="0x8602" name="GRAS_NC_MODE_CNTL"/>
-	<reg32 offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4"/>
-	<reg32 offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4"/>
-	<reg32 offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="4"/>
-	<reg32 offset="0x8e08" name="RB_NC_MODE_CNTL"/>
-	<reg32 offset="0x8e10" name="RB_PERFCTR_RB_SEL" stride="1" length="8"/>
-	<reg32 offset="0x8e18" name="RB_PERFCTR_CCU_SEL" stride="1" length="5"/>
-	<reg32 offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4"/>
-	<reg32 offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6"/>
-	<reg32 offset="0x8e3b" name="RB_RB_SUB_BLOCK_SEL_CNTL_HOST"/>
-	<reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
-	<reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE"/>
-	<reg32 offset="0x960b" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12"/>
-	<reg32 offset="0x9e42" name="PC_PERFCTR_PC_SEL" stride="1" length="16"/>
-	<reg32 offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="16"/>
-	<reg32 offset="0xae02" name="SP_NC_MODE_CNTL"/>
-	<reg32 offset="0xae60" name="SP_PERFCTR_HLSQ_SEL" stride="1" length="6"/>
-	<reg32 offset="0xae6d" name="SP_READ_SEL"/>
-	<reg32 offset="0xae80" name="SP_PERFCTR_SP_SEL" stride="1" length="36"/>
-	<reg32 offset="0xb604" name="TPL1_NC_MODE_CNTL"/>
-	<reg32 offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="18"/>
-	<reg32 offset="0xc000" name="SP_AHB_READ_APERTURE"/>
-	<reg32 offset="0xf400" name="RBBM_SECVID_TRUST_CNTL"/>
-	<reg64 offset="0xf800" name="RBBM_SECVID_TSB_TRUSTED_BASE"/>
-	<reg32 offset="0xf802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
-	<reg32 offset="0xf803" name="RBBM_SECVID_TSB_CNTL"/>
-	<reg64 offset="0xfc00" name="RBBM_SECVID_TSB_STATUS"/>
-</domain>
-
-</database>