diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 7b5b12a88ca..98d2dc8a01f 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -79,6 +79,7 @@ static const driOptionDescription anv_dri_options[] = {
DRI_CONF_ANV_QUERY_CLEAR_WITH_BLORP_THRESHOLD(6)
DRI_CONF_ANV_QUERY_COPY_WITH_SHADER_THRESHOLD(6)
DRI_CONF_ANV_FORCE_INDIRECT_DESCRIPTORS(false)
+ DRI_CONF_SHADER_SPILLING_RATE(0)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
@@ -1373,6 +1374,8 @@ anv_physical_device_try_create(struct vk_instance *vk_instance,
device->compiler->indirect_ubos_use_sampler = device->info.ver < 12;
device->compiler->extended_bindless_surface_offset = device->uses_ex_bso;
device->compiler->use_bindless_sampler_offset = !device->indirect_descriptors;
+ device->compiler->spilling_rate =
+ driQueryOptioni(&instance->dri_options, "shader_spilling_rate");
isl_device_init(&device->isl_dev, &device->info);
device->isl_dev.buffer_length_in_aux_addr = true;
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index bdcb9eb10cf..1a27dc254b4 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -712,6 +712,9 @@ anv_pipeline_hash_common(struct mesa_sha1 *ctx,
const bool rba = device->robust_buffer_access;
_mesa_sha1_update(ctx, &rba, sizeof(rba));
+
+ const int spilling_rate = device->physical->compiler->spilling_rate;
+ _mesa_sha1_update(ctx, &spilling_rate, sizeof(spilling_rate));
}
static void
diff --git a/src/util/00-mesa-defaults.conf b/src/util/00-mesa-defaults.conf
index 24cc2888755..271d5135243 100644
--- a/src/util/00-mesa-defaults.conf
+++ b/src/util/00-mesa-defaults.conf
@@ -1079,6 +1079,15 @@ TODO: document the other workarounds.
+
+
+
+