From 56adf421107d335fa56bbf4370b8dfbfe8642dd5 Mon Sep 17 00:00:00 2001
From: Rohan Garg <rohan.garg@intel.com>
Date: Thu, 4 Apr 2024 11:51:27 +0200
Subject: [PATCH] intel/brw: lower math op regions for Xe2+

This helps fix:
  - dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_3.tan_frag
  - dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_2.tan_frag

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31218>
---
 src/intel/compiler/brw_fs_lower_regioning.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_fs_lower_regioning.cpp b/src/intel/compiler/brw_fs_lower_regioning.cpp
index 7307ec9d6f2..2364ed1c3f9 100644
--- a/src/intel/compiler/brw_fs_lower_regioning.cpp
+++ b/src/intel/compiler/brw_fs_lower_regioning.cpp
@@ -310,7 +310,7 @@ namespace {
          return true;
       }
 
-      if (is_send(inst) || inst->is_math() || inst->is_control_source(i) ||
+      if (is_send(inst) || inst->is_control_source(i) ||
           inst->opcode == BRW_OPCODE_DPAS) {
          return false;
       }
@@ -335,7 +335,7 @@ namespace {
    has_invalid_dst_region(const intel_device_info *devinfo,
                           const fs_inst *inst)
    {
-      if (is_send(inst) || inst->is_math()) {
+      if (is_send(inst)) {
          return false;
       } else {
          const brw_reg_type exec_type = get_exec_type(inst);