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vk/graphics_state, tu: Rewrite renderpass flags handling

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Before this, the render pass code or the driver combined the pipeline
create flags and the implicit flags from the render pass, but the
pipeline create flags will need to be sanitized when they are dynamic
state, so we need to do it in vk_graphics_state where we know that
information.

We also weren't combining pipeline flags correctly when linking, which
on turnip was being hidden by the lack of sanitizing for driver-provided
flags. We can't combine them correctly if they're part of the render
pass state, so they need to be pulled out into the overall pipeline
state.

For drivers using emulated renderpasses or tracking feedback loop
information themselves, this won't make a difference, but we have to
adapt turnip to not pass pipeline flags. This also means that we can
drop all handling of feedback_loop_input_only in turnip and just set it
in the runtime.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25436>
This commit is contained in:
Connor Abbott
2023-05-24 19:33:38 +02:00
committed by Marge Bot
parent 2b62d90158
commit 55f3f952aa
12 changed files with 112 additions and 81 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/vulkan/anv_pipeline.c
+4 -2
View File
@@ -3050,7 +3050,8 @@ anv_graphics_lib_pipeline_create(struct anv_device *device,
result = vk_graphics_pipeline_state_fill(&device->vk,
&pipeline->state, pCreateInfo,
NULL /* sp_info */,
NULL /* driver_rp */,
0 /* driver_rp_flags */,
&pipeline->all_state, NULL, 0, NULL);
if (result != VK_SUCCESS) {
anv_pipeline_finish(&pipeline->base.base, device);
@@ -3166,7 +3167,8 @@ anv_graphics_pipeline_create(struct anv_device *device,
}
result = vk_graphics_pipeline_state_fill(&device->vk, &state, pCreateInfo,
NULL /* sp_info */,
NULL /* driver_rp */,
0 /* driver_rp_flags */,
&all, NULL, 0, NULL);
if (result != VK_SUCCESS) {
anv_pipeline_finish(&pipeline->base.base, device);
src/intel/vulkan/genX_pipeline.c
+8 -8
View File
@@ -1484,9 +1484,9 @@ emit_3dstate_gs(struct anv_graphics_pipeline *pipeline)
}
static bool
rp_has_ds_self_dep(const struct vk_render_pass_state *rp)
state_has_ds_self_dep(const struct vk_graphics_pipeline_state *state)
{
return rp->pipeline_flags &
return state->pipeline_flags &
VK_PIPELINE_CREATE_2_DEPTH_STENCIL_ATTACHMENT_FEEDBACK_LOOP_BIT_EXT;
}
@@ -1608,7 +1608,7 @@ emit_3dstate_ps(struct anv_graphics_pipeline *pipeline,
static void
emit_3dstate_ps_extra(struct anv_graphics_pipeline *pipeline,
const struct vk_rasterization_state *rs,
const struct vk_render_pass_state *rp)
const struct vk_graphics_pipeline_state *state)
{
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
@@ -1633,7 +1633,7 @@ emit_3dstate_ps_extra(struct anv_graphics_pipeline *pipeline,
* around to fetching from the input attachment and we may get the depth
* or stencil value from the current draw rather than the previous one.
*/
ps.PixelShaderKillsPixel = rp_has_ds_self_dep(rp) ||
ps.PixelShaderKillsPixel = state_has_ds_self_dep(state) ||
wm_prog_data->uses_kill;
ps.PixelShaderComputesStencil = wm_prog_data->computed_stencil;
@@ -1678,7 +1678,7 @@ emit_3dstate_vf_statistics(struct anv_graphics_pipeline *pipeline)
static void
compute_kill_pixel(struct anv_graphics_pipeline *pipeline,
const struct vk_multisample_state *ms,
const struct vk_render_pass_state *rp)
const struct vk_graphics_pipeline_state *state)
{
if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
pipeline->kill_pixel = false;
@@ -1702,7 +1702,7 @@ compute_kill_pixel(struct anv_graphics_pipeline *pipeline,
* of an alpha test.
*/
pipeline->kill_pixel =
rp_has_ds_self_dep(rp) ||
state_has_ds_self_dep(state) ||
wm_prog_data->uses_kill ||
wm_prog_data->uses_omask ||
(ms && ms->alpha_to_coverage_enable);
@@ -1905,7 +1905,7 @@ genX(graphics_pipeline_emit)(struct anv_graphics_pipeline *pipeline,
emit_rs_state(pipeline, state->ia, state->rs, state->ms, state->rp,
urb_deref_block_size);
emit_ms_state(pipeline, state->ms);
compute_kill_pixel(pipeline, state->ms, state->rp);
compute_kill_pixel(pipeline, state->ms, state);
emit_3dstate_clip(pipeline, state->ia, state->vp, state->rs);
@@ -2003,7 +2003,7 @@ genX(graphics_pipeline_emit)(struct anv_graphics_pipeline *pipeline,
emit_3dstate_wm(pipeline, state->ia, state->rs,
state->ms, state->cb, state->rp);
emit_3dstate_ps(pipeline, state->ms, state->cb);
emit_3dstate_ps_extra(pipeline, state->rs, state->rp);
emit_3dstate_ps_extra(pipeline, state->rs, state);
}
#if GFX_VERx10 >= 125
src/intel/vulkan_hasvk/anv_pipeline.c
+2 -1
View File
@@ -1867,7 +1867,8 @@ anv_graphics_pipeline_create(struct anv_device *device,
struct vk_graphics_pipeline_all_state all;
struct vk_graphics_pipeline_state state = { };
result = vk_graphics_pipeline_state_fill(&device->vk, &state, pCreateInfo,
NULL /* sp_info */,
NULL /* driver_rp */,
0 /* driver_rp_flags */,
&all, NULL, 0, NULL);
if (result != VK_SUCCESS) {
vk_free2(&device->vk.alloc, pAllocator, pipeline);
src/intel/vulkan_hasvk/genX_pipeline.c
+11 -11
View File
@@ -1541,9 +1541,9 @@ emit_3dstate_gs(struct anv_graphics_pipeline *pipeline,
}
static bool
rp_has_ds_self_dep(const struct vk_render_pass_state *rp)
state_has_ds_self_dep(const struct vk_graphics_pipeline_state *state)
{
return rp->pipeline_flags &
return state->pipeline_flags &
VK_PIPELINE_CREATE_DEPTH_STENCIL_ATTACHMENT_FEEDBACK_LOOP_BIT_EXT;
}
@@ -1553,7 +1553,7 @@ emit_3dstate_wm(struct anv_graphics_pipeline *pipeline,
const struct vk_rasterization_state *rs,
const struct vk_multisample_state *ms,
const struct vk_color_blend_state *cb,
const struct vk_render_pass_state *rp)
const struct vk_graphics_pipeline_state *state)
{
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
@@ -1612,7 +1612,7 @@ emit_3dstate_wm(struct anv_graphics_pipeline *pipeline,
* may get the depth or stencil value from the current draw rather
* than the previous one.
*/
wm.PixelShaderKillsPixel = rp_has_ds_self_dep(rp) ||
wm.PixelShaderKillsPixel = state_has_ds_self_dep(state) ||
wm_prog_data->uses_kill ||
wm_prog_data->uses_omask;
@@ -1744,7 +1744,7 @@ emit_3dstate_ps(struct anv_graphics_pipeline *pipeline,
static void
emit_3dstate_ps_extra(struct anv_graphics_pipeline *pipeline,
const struct vk_rasterization_state *rs,
const struct vk_render_pass_state *rp)
const struct vk_graphics_pipeline_state *state)
{
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
@@ -1769,7 +1769,7 @@ emit_3dstate_ps_extra(struct anv_graphics_pipeline *pipeline,
* around to fetching from the input attachment and we may get the depth
* or stencil value from the current draw rather than the previous one.
*/
ps.PixelShaderKillsPixel = rp_has_ds_self_dep(rp) ||
ps.PixelShaderKillsPixel = state_has_ds_self_dep(state) ||
wm_prog_data->uses_kill;
ps.PixelShaderUsesInputCoverageMask = wm_prog_data->uses_sample_mask;
@@ -1788,7 +1788,7 @@ emit_3dstate_vf_statistics(struct anv_graphics_pipeline *pipeline)
static void
compute_kill_pixel(struct anv_graphics_pipeline *pipeline,
const struct vk_multisample_state *ms,
const struct vk_render_pass_state *rp)
const struct vk_graphics_pipeline_state *state)
{
if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
pipeline->kill_pixel = false;
@@ -1812,7 +1812,7 @@ compute_kill_pixel(struct anv_graphics_pipeline *pipeline,
* of an alpha test.
*/
pipeline->kill_pixel =
rp_has_ds_self_dep(rp) ||
state_has_ds_self_dep(state) ||
wm_prog_data->uses_kill ||
wm_prog_data->uses_omask ||
(ms && ms->alpha_to_coverage_enable);
@@ -1830,7 +1830,7 @@ genX(graphics_pipeline_emit)(struct anv_graphics_pipeline *pipeline,
urb_deref_block_size);
emit_ms_state(pipeline, state->ms);
emit_cb_state(pipeline, state->cb, state->ms);
compute_kill_pixel(pipeline, state->ms, state->rp);
compute_kill_pixel(pipeline, state->ms, state);
emit_3dstate_clip(pipeline, state->ia, state->vp, state->rs);
@@ -1865,10 +1865,10 @@ genX(graphics_pipeline_emit)(struct anv_graphics_pipeline *pipeline,
emit_3dstate_sbe(pipeline);
emit_3dstate_wm(pipeline, state->ia, state->rs,
state->ms, state->cb, state->rp);
state->ms, state->cb, state);
emit_3dstate_ps(pipeline, state->ms, state->cb);
#if GFX_VER >= 8
emit_3dstate_ps_extra(pipeline, state->rs, state->rp);
emit_3dstate_ps_extra(pipeline, state->rs, state);
#endif
}