From 526c1889e5d591da5c71caca5699f51e1f129be4 Mon Sep 17 00:00:00 2001 From: Iago Toral Quiroga Date: Mon, 22 Nov 2021 12:56:03 +0100 Subject: [PATCH] broadcom/compiler: update thread end restrictions for v7.x MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In 4.x it is not allowed to write to the register file in the last 3 instructions, but in 7.x we only have this restriction in the thread end instruction itself, and only if the write comes from the ALU ports. Reviewed-by: Alejandro Piñeiro Part-of: --- src/broadcom/compiler/qpu_schedule.c | 31 ++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/src/broadcom/compiler/qpu_schedule.c b/src/broadcom/compiler/qpu_schedule.c index 4e32585b004..ffad1d8d4ec 100644 --- a/src/broadcom/compiler/qpu_schedule.c +++ b/src/broadcom/compiler/qpu_schedule.c @@ -1938,17 +1938,30 @@ qpu_inst_valid_in_thrend_slot(struct v3d_compile *c, return false; } - /* No writing physical registers at the end. */ - bool add_is_nop = inst->alu.add.op == V3D_QPU_A_NOP; - bool mul_is_nop = inst->alu.mul.op == V3D_QPU_M_NOP; - if ((!add_is_nop && !inst->alu.add.magic_write) || - (!mul_is_nop && !inst->alu.mul.magic_write)) { - return false; + if (c->devinfo->ver <= 42) { + /* No writing physical registers at the end. */ + bool add_is_nop = inst->alu.add.op == V3D_QPU_A_NOP; + bool mul_is_nop = inst->alu.mul.op == V3D_QPU_M_NOP; + if ((!add_is_nop && !inst->alu.add.magic_write) || + (!mul_is_nop && !inst->alu.mul.magic_write)) { + return false; + } + + if (v3d_qpu_sig_writes_address(c->devinfo, &inst->sig) && + !inst->sig_magic) { + return false; + } } - if (v3d_qpu_sig_writes_address(c->devinfo, &inst->sig) && - !inst->sig_magic) { - return false; + if (c->devinfo->ver >= 71) { + /* The thread end instruction must not write to the + * register file via the add/mul ALUs. + */ + if (slot == 0 && + (!inst->alu.add.magic_write || + !inst->alu.mul.magic_write)) { + return false; + } } if (c->devinfo->ver < 40 && inst->alu.add.op == V3D_QPU_A_SETMSF)