diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 4bfe6d3f894..6f3434ae2ed 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -1716,18 +1716,8 @@ brw_broadcast(struct brw_codegen *p,
    assert(src.file == FIXED_GRF &&
           src.address_mode == BRW_ADDRESS_DIRECT);
    assert(!src.abs && !src.negate);
-
-   /* Gen12.5 adds the following region restriction:
-    *
-    *    "Vx1 and VxH indirect addressing for Float, Half-Float, Double-Float
-    *    and Quad-Word data must not be used."
-    *
-    * We require the source and destination types to match so stomp to an
-    * unsigned integer type.
-    */
+   assert(brw_type_is_uint(src.type));
    assert(src.type == dst.type);
-   src.type = dst.type =
-      brw_type_with_size(BRW_TYPE_UD, brw_type_size_bits(src.type));
 
    if ((src.vstride == 0 && src.hstride == 0) ||
        idx.file == IMM) {
diff --git a/src/intel/compiler/brw_generator.cpp b/src/intel/compiler/brw_generator.cpp
index 78e667118b0..c847db1d9fc 100644
--- a/src/intel/compiler/brw_generator.cpp
+++ b/src/intel/compiler/brw_generator.cpp
@@ -202,18 +202,8 @@ brw_generator::generate_mov_indirect(brw_inst *inst,
    assert(indirect_byte_offset.type == BRW_TYPE_UD);
    assert(indirect_byte_offset.file == FIXED_GRF);
    assert(!reg.abs && !reg.negate);
-
-   /* Gen12.5 adds the following region restriction:
-    *
-    *    "Vx1 and VxH indirect addressing for Float, Half-Float, Double-Float
-    *    and Quad-Word data must not be used."
-    *
-    * We require the source and destination types to match so stomp to an
-    * unsigned integer type.
-    */
+   assert(brw_type_is_uint(reg.type));
    assert(reg.type == dst.type);
-   reg.type = dst.type =
-      brw_type_with_size(BRW_TYPE_UD, brw_type_size_bits(reg.type));
 
    unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
 
@@ -337,18 +327,8 @@ brw_generator::generate_shuffle(brw_inst *inst,
     * implement for 64-bit values so we just don't bother.
     */
    assert(devinfo->has_64bit_float || brw_type_size_bytes(src.type) <= 4);
-
-   /* Gen12.5 adds the following region restriction:
-    *
-    *    "Vx1 and VxH indirect addressing for Float, Half-Float, Double-Float
-    *    and Quad-Word data must not be used."
-    *
-    * We require the source and destination types to match so stomp to an
-    * unsigned integer type.
-    */
+   assert(brw_type_is_uint(src.type));
    assert(src.type == dst.type);
-   src.type = dst.type =
-      brw_type_with_size(BRW_TYPE_UD, brw_type_size_bits(src.type));
 
    /* Because we're using the address register, we're limited to 16-wide
     * by the address register file and 8-wide for 64-bit types.  We could try
diff --git a/src/intel/compiler/brw_lower.cpp b/src/intel/compiler/brw_lower.cpp
index 81f1ac6119d..73e7d6b2b0f 100644
--- a/src/intel/compiler/brw_lower.cpp
+++ b/src/intel/compiler/brw_lower.cpp
@@ -727,6 +727,22 @@ brw_lower_alu_restrictions(brw_shader &s)
          }
          break;
 
+      case SHADER_OPCODE_SHUFFLE:
+      case SHADER_OPCODE_MOV_INDIRECT:
+      case SHADER_OPCODE_BROADCAST:
+         /* Gen12.5 adds the following region restriction:
+          *
+          *   "Vx1 and VxH indirect addressing for Float, Half-Float,
+          *    Double-Float and Quad-Word data must not be used."
+          *
+          * We require the source and destination types to match so stomp to
+          * an unsigned integer type.
+          */
+         assert(inst->src[0].type == inst->dst.type);
+         inst->src[0].type = inst->dst.type = brw_type_with_size(BRW_TYPE_UD,
+            brw_type_size_bits(inst->src[0].type));
+         break;
+
       default:
          break;
       }
diff --git a/src/intel/compiler/brw_opt.cpp b/src/intel/compiler/brw_opt.cpp
index 4a4d6f37f8d..60cb838513a 100644
--- a/src/intel/compiler/brw_opt.cpp
+++ b/src/intel/compiler/brw_opt.cpp
@@ -161,8 +161,6 @@ brw_optimize(brw_shader &s)
 
    brw_shader_phase_update(s, BRW_SHADER_PHASE_AFTER_MIDDLE_LOWERING);
 
-   OPT(brw_lower_alu_restrictions);
-
    OPT(brw_opt_combine_constants);
    if (OPT(brw_lower_integer_multiplication)) {
       /* If lower_integer_multiplication made progress, it may have produced
@@ -213,6 +211,8 @@ brw_optimize(brw_shader &s)
 
    OPT(brw_lower_indirect_mov);
 
+   OPT(brw_lower_alu_restrictions);
+
    OPT(brw_lower_find_live_channel);
 
    OPT(brw_lower_load_subgroup_invocation);