From 51f4a2572a05ba8390e4d4e842048e2f2399e895 Mon Sep 17 00:00:00 2001
From: Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com>
Date: Tue, 29 Jul 2025 21:06:16 +0000
Subject: [PATCH] intel/compiler: Initial bits for SRND instruction

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36529>
---
 src/intel/compiler/brw_eu.c          | 1 +
 src/intel/compiler/brw_eu.h          | 3 +++
 src/intel/compiler/brw_eu_defines.h  | 1 +
 src/intel/compiler/brw_eu_emit.c     | 9 +++++++++
 src/intel/compiler/brw_generator.cpp | 5 +++++
 5 files changed, 19 insertions(+)

diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c
index 9cac5dfa1fe..7aa5a6cb0a6 100644
--- a/src/intel/compiler/brw_eu.c
+++ b/src/intel/compiler/brw_eu.c
@@ -641,6 +641,7 @@ static const struct opcode_desc opcode_descs[] = {
    { BRW_OPCODE_SUBB,     79,  "subb",    2,    1,    GFX_ALL },
    { BRW_OPCODE_ADD3,     82,  "add3",    3,    1,    GFX_GE(GFX125) },
    { BRW_OPCODE_DP4,      84,  "dp4",     2,    1,    GFX_LT(GFX11) },
+   { BRW_OPCODE_SRND,     84,  "srnd",    2,    1,    GFX_GE(XE2) },
    { BRW_OPCODE_DPH,      85,  "dph",     2,    1,    GFX_LT(GFX11) },
    { BRW_OPCODE_DP3,      86,  "dp3",     2,    1,    GFX_LT(GFX11) },
    { BRW_OPCODE_DP2,      87,  "dp2",     2,    1,    GFX_LT(GFX11) },
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index ad81180ae7d..504d426c2b1 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -1539,6 +1539,9 @@ brw_eu_inst *brw_DPAS(struct brw_codegen *p, enum gfx12_systolic_depth sdepth,
                    unsigned rcount, struct brw_reg dest, struct brw_reg src0,
                    struct brw_reg src1, struct brw_reg src2);
 
+brw_eu_inst *brw_SRND(struct brw_codegen *p, struct brw_reg dest,
+                   struct brw_reg src0, struct brw_reg src1);
+
 void
 brw_broadcast(struct brw_codegen *p,
               struct brw_reg dst,
diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h
index af11bd27e18..781239687a0 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -218,6 +218,7 @@ enum ENUM_PACKED opcode {
    BRW_OPCODE_SUBB,
    BRW_OPCODE_ADD3, /* Gen12+ only */
    BRW_OPCODE_DP4,
+   BRW_OPCODE_SRND, /* Xe2+ only */
    BRW_OPCODE_DPH,
    BRW_OPCODE_DP3,
    BRW_OPCODE_DP2,
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 0e0064f0c9f..e8a954f1cf7 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -1020,6 +1020,15 @@ brw_DPAS(struct brw_codegen *p, enum gfx12_systolic_depth sdepth,
                              src1, src2);
 }
 
+brw_eu_inst *
+brw_SRND(struct brw_codegen *p, struct brw_reg dest,
+         struct brw_reg src0, struct brw_reg src1)
+{
+   assert(dest.type == BRW_TYPE_HF);
+   assert(src0.type == BRW_TYPE_F);
+   return brw_alu2(p, BRW_OPCODE_SRND, dest, src0, src1);
+}
+
 void brw_NOP(struct brw_codegen *p)
 {
    brw_eu_inst *insn = next_insn(p, BRW_OPCODE_NOP);
diff --git a/src/intel/compiler/brw_generator.cpp b/src/intel/compiler/brw_generator.cpp
index c17b178433f..7250d274226 100644
--- a/src/intel/compiler/brw_generator.cpp
+++ b/src/intel/compiler/brw_generator.cpp
@@ -922,6 +922,11 @@ brw_generator::generate_code(const brw_shader &s,
          brw_DP4A(p, dst, src[0], src[1], src[2]);
          break;
 
+      case BRW_OPCODE_SRND:
+         assert(devinfo->ver >= 20);
+         brw_SRND(p, dst, src[0], src[1]);
+         break;
+
       case BRW_OPCODE_LINE:
          brw_LINE(p, dst, src[0], src[1]);
          break;