From 51a6261d38b2804c2a45f16236b1000b7777c220 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tapani=20P=C3=A4lli?= Date: Fri, 4 Sep 2020 09:56:19 +0300 Subject: [PATCH] iris: remove additional pipe control done before hiz for older gens MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The restriction found in removed comment is not found on new specs. Signed-off-by: Tapani Pälli Reviewed-by: Kenneth Graunke Part-of: --- src/gallium/drivers/iris/iris_resolve.c | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) diff --git a/src/gallium/drivers/iris/iris_resolve.c b/src/gallium/drivers/iris/iris_resolve.c index fba62e3ea35..a5cd7f16b57 100644 --- a/src/gallium/drivers/iris/iris_resolve.c +++ b/src/gallium/drivers/iris/iris_resolve.c @@ -551,26 +551,13 @@ iris_hiz_exec(struct iris_context *ice, * the depth buffer clear operation." * * Same applies for Gen8 and Gen9. - * - * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1 - * PIPE_CONTROL, Depth Cache Flush Enable: - * - * "This bit must not be set when Depth Stall Enable bit is set in - * this packet." - * - * This is confirmed to hold for real, Haswell gets immediate gpu hangs. - * - * Therefore issue two pipe control flushes, one for cache flush and - * another for depth stall. */ iris_emit_pipe_control_flush(batch, - "hiz op: pre-flushes (1/2)", + "hiz op: pre-flush", PIPE_CONTROL_DEPTH_CACHE_FLUSH | + PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_CS_STALL); - iris_emit_pipe_control_flush(batch, "hiz op: pre-flushes (2/2)", - PIPE_CONTROL_DEPTH_STALL); - assert(isl_aux_usage_has_hiz(res->aux.usage) && res->aux.bo); iris_batch_maybe_flush(batch, 1500);