From 512b43317274818bc32d90851c8b9ca16835aeaf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Date: Tue, 3 Dec 2024 09:47:55 -0800 Subject: [PATCH] intel/hwconfig: Sync hwconfig with IGT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit intel-gpu-tools have a few more entries in enum intel_hwconfig, so adding the missing ones to Mesa. Reviewed-by: Lionel Landwerlin Signed-off-by: José Roberto de Souza Part-of: --- src/intel/dev/intel_hwconfig.c | 10 ++++++++++ src/intel/dev/intel_hwconfig_types.h | 21 ++++++++++++++++++--- 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/src/intel/dev/intel_hwconfig.c b/src/intel/dev/intel_hwconfig.c index 2b2c6b3052e..1f4e17677bb 100644 --- a/src/intel/dev/intel_hwconfig.c +++ b/src/intel/dev/intel_hwconfig.c @@ -117,6 +117,16 @@ key_to_name(uint32_t key) HANDLE(INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE); HANDLE(INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB); HANDLE(INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB); + HANDLE(INTEL_HWCONFIG_NUM_HBM_STACKS_PER_TILE); + HANDLE(INTEL_HWCONFIG_NUM_CHANNELS_PER_HBM_STACK); + HANDLE(INTEL_HWCONFIG_HBM_CHANNEL_WIDTH_IN_BYTES); + HANDLE(INTEL_HWCONFIG_MIN_TASK_URB_ENTRIES); + HANDLE(INTEL_HWCONFIG_MAX_TASK_URB_ENTRIES); + HANDLE(INTEL_HWCONFIG_MIN_MESH_URB_ENTRIES); + HANDLE(INTEL_HWCONFIG_MAX_MESH_URB_ENTRIES); + HANDLE(INTEL_HWCONFIG_MAX_GSC); + HANDLE(INTEL_HWCONFIG_SYNC_NUM_RT_STACKS_PER_DSS); + HANDLE(INTEL_HWCONFIG_NUM_XECU); #undef HANDLE } return "UNKNOWN_INTEL_HWCONFIG"; diff --git a/src/intel/dev/intel_hwconfig_types.h b/src/intel/dev/intel_hwconfig_types.h index e198ae056ff..4f3c34a9c4f 100644 --- a/src/intel/dev/intel_hwconfig_types.h +++ b/src/intel/dev/intel_hwconfig_types.h @@ -87,18 +87,33 @@ enum intel_hwconfig { INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE, /* 71 */ INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB, /* 72 */ INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB, /* 73 */ + INTEL_HWCONFIG_NUM_HBM_STACKS_PER_TILE, /* 74 */ + INTEL_HWCONFIG_NUM_CHANNELS_PER_HBM_STACK, /* 75 */ + INTEL_HWCONFIG_HBM_CHANNEL_WIDTH_IN_BYTES, /* 76 */ + INTEL_HWCONFIG_MIN_TASK_URB_ENTRIES, /* 77 */ + INTEL_HWCONFIG_MAX_TASK_URB_ENTRIES, /* 78 */ + INTEL_HWCONFIG_MIN_MESH_URB_ENTRIES, /* 79 */ + INTEL_HWCONFIG_MAX_MESH_URB_ENTRIES, /* 80 */ + INTEL_HWCONFIG_MAX_GSC, /* 81 */ + INTEL_HWCONFIG_SYNC_NUM_RT_STACKS_PER_DSS, /* 82 */ + INTEL_HWCONFIG_NUM_XECU, /* 83 */ __INTEL_HWCONFIG_LIMIT }; enum { INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4 = 0, INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5, + INTEL_HWCONFIG_MEMORY_TYPE_HBM2, + INTEL_HWCONFIG_MEMORY_TYPE_HBM2e, + INTEL_HWCONFIG_MEMORY_TYPE_GDDR6, + __INTEL_HWCONFIG_MEMORY_TYPE_LIMIT }; enum { - INTEL_HWCONFIG_CACHE_TYPE_L3 = 1 << 0, - INTEL_HWCONFIG_CACHE_TYPE_LLC = 1 << 1, - INTEL_HWCONFIG_CACHE_TYPE_EDRAM = 1 << 2, + INTEL_HWCONFIG_CACHE_TYPE_L3 = 0, + INTEL_HWCONFIG_CACHE_TYPE_LLC, + INTEL_HWCONFIG_CACHE_TYPE_EDRAM, + __INTEL_HWCONFIG_CACHE_TYPE_LIMIT }; #endif /* _INTEL_HWCONFIG_TYPES_H_ */