From 50daf161f45bef680d23c4909631db3607c748a6 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Wed, 4 Jan 2023 12:52:07 -0800 Subject: [PATCH] intel/brw/xe2+: Lower 64-bit integer uadd_sat. Fixes failures of CTS tests that currently end up emitting 64-bit integer ADDs with saturation, which isn't supported by the hardware. Reviewed-by: Ian Romanick Part-of: --- src/intel/compiler/brw_compiler.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index 35979d010ea..3a61af00211 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -145,7 +145,8 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo) nir_lower_bit_count64 | nir_lower_bcsel64 | nir_lower_conv64 | nir_lower_extract64 | nir_lower_scan_reduce_bitwise64 | - nir_lower_scan_reduce_iadd64 | nir_lower_subgroup_shuffle64); + nir_lower_scan_reduce_iadd64 | nir_lower_subgroup_shuffle64 | + nir_lower_iadd_sat64 | nir_lower_uadd_sat64); /* We want the GLSL compiler to emit code that uses condition codes */ for (int i = 0; i < MESA_ALL_SHADER_STAGES; i++) {