From 50967402cc2ca47d61f99c688f87e2250d3cd748 Mon Sep 17 00:00:00 2001
From: Nanley Chery <nanley.g.chery@intel.com>
Date: Wed, 8 Dec 2021 13:28:46 -0500
Subject: [PATCH] intel/isl: Require Y-tiling for depth on gfx4-5

This enables isl_surf_get_hiz_surf to be simplified.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14091>
---
 src/intel/isl/isl_gfx4.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/intel/isl/isl_gfx4.c b/src/intel/isl/isl_gfx4.c
index 8ad3f6152e7..8b716c615ec 100644
--- a/src/intel/isl/isl_gfx4.c
+++ b/src/intel/isl/isl_gfx4.c
@@ -56,10 +56,10 @@ isl_gfx4_filter_tiling(const struct isl_device *dev,
        *    BWT014   The Depth Buffer Must be Tiled, it cannot be linear. This
        *    field must be set to 1 on DevBW-A.  [DevBW -A,B]
        *
-       * In testing, the linear configuration doesn't seem to work on gfx4.
+       * In testing, the linear configuration doesn't seem to work on I965. We
+       * choose to be consistent and require tiling for gfx4-5.
        */
-      *flags &= (ISL_GFX_VER(dev) == 4 && !ISL_DEV_IS_G4X(dev)) ?
-                ISL_TILING_Y0_BIT : (ISL_TILING_Y0_BIT | ISL_TILING_LINEAR_BIT);
+      *flags &= ISL_TILING_Y0_BIT;
    }
 
    if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT) {