diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 6ab6280bf61..aaeb04b429c 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -5512,7 +5512,7 @@ radv_get_buffer_memory_requirements(struct radv_device *device, VkDeviceSize siz
    pMemoryRequirements->memoryRequirements.memoryTypeBits =
       ((1u << device->physical_device->memory_properties.memoryTypeCount) - 1u) &
       ~device->physical_device->memory_types_32bit;
-   
+
    /* Allow 32-bit address-space for DGC usage, as this buffer will contain
     * cmd buffer upload buffers, and those get passed to shaders through 32-bit
     * pointers.
diff --git a/src/amd/vulkan/radv_device_generated_commands.c b/src/amd/vulkan/radv_device_generated_commands.c
index c60ec0a1ef0..3d1039a5fd3 100644
--- a/src/amd/vulkan/radv_device_generated_commands.c
+++ b/src/amd/vulkan/radv_device_generated_commands.c
@@ -370,7 +370,6 @@ build_dgc_prepare_shader(struct radv_device *dev)
       nir_store_var(&b, cmd_buf.offset, nir_imul(&b, global_id, cmd_buf_stride), 1);
       nir_ssa_def *cmd_buf_end = nir_iadd(&b, nir_load_var(&b, cmd_buf.offset), cmd_buf_stride);
 
-      
       nir_ssa_def *stream_buf = radv_meta_load_descriptor(&b, 0, DGC_DESC_STREAM);
       nir_ssa_def *stream_base = nir_imul(&b, sequence_id, stream_stride);