From 4ec43c59da8f8f03a27f2ac4ea2481586071c3fc Mon Sep 17 00:00:00 2001 From: David Rosca Date: Tue, 5 Nov 2024 15:59:57 +0100 Subject: [PATCH] radeonsi/vcn: Use correct frame context buffer for preencode on VCN5 Fixes: 3c5fe03b92c ("radeonsi/vcn: Add support for VCN5 dpb tier2") Reviewed-by: Ruijing Dong Part-of: --- src/gallium/drivers/radeonsi/radeon_vcn_enc_5_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc_5_0.c b/src/gallium/drivers/radeonsi/radeon_vcn_enc_5_0.c index 520e48432ad..63d588ce7b6 100644 --- a/src/gallium/drivers/radeonsi/radeon_vcn_enc_5_0.c +++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc_5_0.c @@ -341,7 +341,7 @@ static void radeon_enc_ctx_tier2(struct radeon_encoder *enc) continue; } struct rvid_buffer *pre = enc->enc_pic.dpb_bufs[i]->pre; - struct rvid_buffer *pre_fcb = enc->enc_pic.dpb_bufs[i]->fcb; + struct rvid_buffer *pre_fcb = enc->enc_pic.dpb_bufs[i]->pre_fcb; RADEON_ENC_READWRITE(pre->res->buf, pre->res->domains, 0); RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch); RADEON_ENC_READWRITE(pre->res->buf, pre->res->domains, enc->enc_pic.dpb_luma_size);