From 4de638ae1e9ecc518e6a0c9d4fb0cd6e160ae136 Mon Sep 17 00:00:00 2001 From: Nanley Chery Date: Tue, 12 Nov 2024 08:11:23 -0500 Subject: [PATCH] intel: Enable CCS_E on linear surfaces on Xe2+ Allow CCS for non-display linear surfaces in isl_surf_supports_ccs(). We're going to rely more on the helper to determine CCS-enabling for Xe2 on iris. Reviewed-by: Jianxun Zhang Part-of: --- src/intel/blorp/blorp_blit.c | 2 +- src/intel/blorp/blorp_clear.c | 2 +- src/intel/isl/isl.c | 50 +++++++++++++++++++++--------- src/intel/vulkan/anv_image.c | 7 ++--- src/intel/vulkan/genX_cmd_buffer.c | 6 ++-- 5 files changed, 42 insertions(+), 25 deletions(-) diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c index 191af2db3d4..56a89a81501 100644 --- a/src/intel/blorp/blorp_blit.c +++ b/src/intel/blorp/blorp_blit.c @@ -1630,7 +1630,7 @@ blorp_surf_convert_to_single_slice(const struct isl_device *isl_dev, bool ok UNUSED; /* It would be insane to try and do this on a compressed surface */ - assert(info->aux_usage == ISL_AUX_USAGE_NONE); + assert(info->aux_surf.size_B == 0); /* Just bail if we have nothing to do. */ if (info->surf.dim == ISL_SURF_DIM_2D && diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c index d400a6b4bf7..968374bf4d8 100644 --- a/src/intel/blorp/blorp_clear.c +++ b/src/intel/blorp/blorp_clear.c @@ -840,7 +840,7 @@ blorp_clear(struct blorp_batch *batch, assert(params.dst.surf.levels == 1); assert(params.dst.surf.samples == 1); assert(params.dst.tile_x_sa == 0 || params.dst.tile_y_sa == 0); - assert(params.dst.aux_usage == ISL_AUX_USAGE_NONE); + assert(params.dst.aux_surf.size_B == 0); /* max_image_width rounded down to a multiple of 3 */ const unsigned max_fake_rgb_width = (max_image_width / 3) * 3; diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 234e2fe7c9c..4bf2929b1f4 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -3736,6 +3736,12 @@ _isl_surf_info_supports_ccs(const struct isl_device *dev, if (ISL_GFX_VER(dev) <= 11 && isl_surf_usage_is_depth_or_stencil(usage)) return false; + /* If the surface will be used for transfering data between the GPU and + * CPU, compression would only introduce expensive resolves. + */ + if (usage & ISL_SURF_USAGE_STAGING_BIT) + return false; + if (usage & ISL_SURF_USAGE_DISABLE_AUX_BIT) return false; @@ -3753,21 +3759,35 @@ isl_surf_supports_ccs(const struct isl_device *dev, if (!_isl_surf_info_supports_ccs(dev, surf->format, surf->usage)) return false; - /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render - * Target(s)", beneath the "Fast Color Clear" bullet (p326): - * - * - Support is limited to tiled render targets. - * - * From the BSpec (44930) for Gfx12: - * - * Linear CCS is only allowed for Untyped Buffers but only via HDC - * Data-Port messages. - * - * We never use untyped messages on surfaces created by ISL on Gfx9+ so - * this means linear is out on Gfx12+ as well. - */ - if (surf->tiling == ISL_TILING_LINEAR) - return false; + if (surf->tiling == ISL_TILING_LINEAR) { + /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render + * Target(s)", beneath the "Fast Color Clear" bullet (p326): + * + * - Support is limited to tiled render targets. + * + * From the BSpec 44930 (r47128) for Gfx12: + * + * Linear CCS is only allowed for Untyped Buffers but only via HDC + * Data-Port messages. + * + * We never use untyped messages on surfaces created by ISL on Gfx9+ so + * this means linear is out on Gfx12 as well. + */ + if (ISL_GFX_VER(dev) <= 12) + return false; + + /* From the Bspec 71650 (r59764) for Xe2: + * + * 3 SW must disable or resolve compression + * Display: Access to anything except Tile4 Framebuffers... + * [...] + * Linear/TileX Framebuffers + * + * Instead of resolving, disable compression on linear display surfaces. + */ + if (isl_surf_usage_is_display(surf->usage)) + return false; + } /* From the SKL PRMs, Volume 7: MCS Buffer for Render Target(s), * diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c index 8d6b74a8bb6..005a6b619db 100644 --- a/src/intel/vulkan/anv_image.c +++ b/src/intel/vulkan/anv_image.c @@ -3120,9 +3120,6 @@ anv_layout_to_aux_state(const struct intel_device_info * const devinfo, const enum isl_aux_usage aux_usage = image->planes[plane].aux_usage; assert(aux_usage != ISL_AUX_USAGE_NONE); - /* All images that use an auxiliary surface are required to be tiled. */ - assert(image->planes[plane].primary_surface.isl.tiling != ISL_TILING_LINEAR); - /* Handle a few special cases */ switch (layout) { /* Invalid layouts */ @@ -3132,8 +3129,8 @@ anv_layout_to_aux_state(const struct intel_device_info * const devinfo, /* Undefined layouts * * The pre-initialized layout is equivalent to the undefined layout for - * optimally-tiled images. We can only do color compression (CCS or HiZ) - * on tiled images. + * optimally-tiled images and for images not bound to host-visible memory. + * We only do compression on images that have one or both properties. */ case VK_IMAGE_LAYOUT_UNDEFINED: case VK_IMAGE_LAYOUT_PREINITIALIZED: diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index ba24de59067..f07ea254641 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1171,9 +1171,9 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer, final_fast_clear : ANV_FAST_CLEAR_NONE; } - assert(image->planes[plane].primary_surface.isl.tiling != ISL_TILING_LINEAR); - - /* The following layouts are equivalent for non-linear images. */ + /* The following layouts are equivalent for non-linear images and + * for images not bound to host-visible memory. + */ const bool initial_layout_undefined = initial_layout == VK_IMAGE_LAYOUT_UNDEFINED || initial_layout == VK_IMAGE_LAYOUT_PREINITIALIZED;