From 4d381c9136f30050f7d6d406ef9508a880003db2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 18 Dec 2025 22:44:30 -0600 Subject: [PATCH] ac/nir/lower_taskmesh_io_to_mem: Don't hardcode payload entry size in shaders MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently the number of task payload entry size is hardcoded in shaders as a constant. This isn't a good idea because it makes the code inflexible, eg. doesn't allow us to change the number of entries dynamically. Signed-off-by: Timur Kristóf Reviewed-by: Qiang Yu Reviewed-by: Marek Olšák Part-of: --- .../nir/ac_nir_lower_taskmesh_io_to_mem.c | 22 ++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/src/amd/common/nir/ac_nir_lower_taskmesh_io_to_mem.c b/src/amd/common/nir/ac_nir_lower_taskmesh_io_to_mem.c index 61132208f16..ec990899bc5 100644 --- a/src/amd/common/nir/ac_nir_lower_taskmesh_io_to_mem.c +++ b/src/amd/common/nir/ac_nir_lower_taskmesh_io_to_mem.c @@ -17,7 +17,6 @@ */ typedef struct { - unsigned payload_entry_bytes; unsigned draw_entry_bytes; /* True if the lowering needs to insert shader query. */ @@ -33,6 +32,21 @@ task_num_entries(nir_builder *b, return nir_udiv_imm(b, bytes, s->draw_entry_bytes); } +static nir_def * +task_payload_entry_bytes(nir_builder *b, + lower_tsms_io_state *s) +{ + nir_def *num_entries = task_num_entries(b, s); + nir_def *ring = nir_load_ring_task_payload_amd(b); + nir_def *bytes = nir_channel(b, ring, 2); + + /* num_entries must be a power of two, + * use that to implement a division using a shift. + */ + nir_def *lsb = nir_find_lsb(b, num_entries); + return nir_ushr(b, bytes, lsb); +} + static nir_def * task_workgroup_index(nir_builder *b, lower_tsms_io_state *s) @@ -233,7 +247,7 @@ lower_task_payload_store(nir_builder *b, nir_def *addr = intrin->src[1].ssa; nir_def *ring = nir_load_ring_task_payload_amd(b); nir_def *ptr = task_ring_entry_index(b, s); - nir_def *ring_off = nir_imul_imm(b, ptr, s->payload_entry_bytes); + nir_def *ring_off = nir_imul(b, ptr, task_payload_entry_bytes(b, s)); nir_def *zero = nir_imm_int(b, 0); nir_store_buffer_amd(b, store_val, ring, addr, ring_off, zero, .base = base, @@ -260,7 +274,7 @@ lower_taskmesh_payload_load(nir_builder *b, nir_def *addr = intrin->src[0].ssa; nir_def *ring = nir_load_ring_task_payload_amd(b); - nir_def *ring_off = nir_imul_imm(b, ptr, s->payload_entry_bytes); + nir_def *ring_off = nir_imul(b, ptr, task_payload_entry_bytes(b, s)); nir_def *zero = nir_imm_int(b, 0); return nir_load_buffer_amd(b, num_components, bit_size, ring, addr, ring_off, zero, .base = base, @@ -308,7 +322,6 @@ ac_nir_lower_task_outputs_to_mem(nir_shader *shader, lower_tsms_io_state state = { .draw_entry_bytes = 16, - .payload_entry_bytes = task_payload_entry_bytes, .has_query = has_query, }; @@ -363,7 +376,6 @@ ac_nir_lower_mesh_inputs_to_mem(nir_shader *shader, lower_tsms_io_state state = { .draw_entry_bytes = 16, - .payload_entry_bytes = task_payload_entry_bytes, }; return nir_shader_lower_instructions(shader,