diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h
index 65c9f8fe4f9..d859cd1dd55 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -720,6 +720,8 @@ enum memory_flags {
    MEMORY_FLAG_INCLUDE_HELPERS = 1 << 1,
    /** Whether memory access is marked volatile by GLSL/SPIR-V. */
    MEMORY_FLAG_VOLATILE_ACCESS = 1 << 2,
+   /** Whether memory access is marked coherent by GLSL/SPIR-V. */
+   MEMORY_FLAG_COHERENT_ACCESS = 1 << 3,
 };
 
 enum rt_logical_srcs {
diff --git a/src/intel/compiler/brw_from_nir.cpp b/src/intel/compiler/brw_from_nir.cpp
index efd95fc1bc4..35fe401b78a 100644
--- a/src/intel/compiler/brw_from_nir.cpp
+++ b/src/intel/compiler/brw_from_nir.cpp
@@ -7101,11 +7101,14 @@ brw_from_nir_emit_memory_access(nir_to_brw_state &ntb,
       (nir_intrinsic_access(instr) & ACCESS_INCLUDE_HELPERS);
    const bool volatile_access = nir_intrinsic_has_access(instr) &&
       (nir_intrinsic_access(instr) & ACCESS_VOLATILE);
+   const bool coherent_access = nir_intrinsic_has_access(instr) &&
+      (nir_intrinsic_access(instr) & ACCESS_COHERENT);
    const unsigned align =
       nir_intrinsic_has_align(instr) ? nir_intrinsic_align(instr) : 0;
    const unsigned logical_flags =
       (include_helpers ? MEMORY_FLAG_INCLUDE_HELPERS : 0) |
-      (volatile_access ? MEMORY_FLAG_VOLATILE_ACCESS : 0);
+      (volatile_access ? MEMORY_FLAG_VOLATILE_ACCESS : 0) |
+      (coherent_access ? MEMORY_FLAG_COHERENT_ACCESS : 0);
    bool no_mask_handle = false;
    int data_src = -1;
 
diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp
index 4687dd1b783..2292be34ccb 100644
--- a/src/intel/compiler/brw_lower_logical_sends.cpp
+++ b/src/intel/compiler/brw_lower_logical_sends.cpp
@@ -1513,6 +1513,7 @@ lower_lsc_memory_logical_send(const brw_builder &bld, brw_inst *inst)
    const bool transpose = flags & MEMORY_FLAG_TRANSPOSE;
    const bool include_helpers = flags & MEMORY_FLAG_INCLUDE_HELPERS;
    const bool volatile_access = flags & MEMORY_FLAG_VOLATILE_ACCESS;
+   const bool coherent_access = flags & MEMORY_FLAG_COHERENT_ACCESS;
    const brw_reg data0 = inst->src[MEMORY_LOGICAL_DATA0];
    const brw_reg data1 = inst->src[MEMORY_LOGICAL_DATA1];
    const bool has_side_effects = inst->has_side_effects();
@@ -1598,6 +1599,10 @@ lower_lsc_memory_logical_send(const brw_builder &bld, brw_inst *inst)
             (lsc_opcode_is_store(op) ?
                LSC_CACHE(devinfo, STORE, L1UC_L3UC) :
                LSC_CACHE(devinfo, LOAD, L1UC_L3UC))) :
+      /* Skip L1 for coherent accesses */
+      coherent_access ? (lsc_opcode_is_store(op) ?
+                         LSC_CACHE(devinfo, STORE, L1UC_L3WB) :
+                         LSC_CACHE(devinfo, LOAD, L1UC_L3C)) :
       lsc_opcode_is_store(op) ? LSC_CACHE(devinfo, STORE, L1STATE_L3MOCS) :
       LSC_CACHE(devinfo, LOAD, L1STATE_L3MOCS);